Vector multiplication with operand base system conversion and re-conversion
A method is described that includes performing the following with an instruction execution pipeline of a semiconductor chip. Multiplying two vectors by: receiving a vector element multiplicand and vector element multiplier expressed in a first base system; converting the vector element multiplicand and vector element multiplier into a second lower base system to form a converted vector element multiplicand and a converted vector element multiplier; multiplying with a first execution unit of the pipeline the converted vector element multiplicand and the converted vector element multiplier to form a multiplication result; accumulating in a register a portion of the multiplication result with a portion of a result of a prior multiplication of operands expressed in the second lower base system; and, converting contents of the register into the first base system.
1. A method comprising:
decoding a single instruction with a hardware decoder of a hardware processor; and
executing the single instruction with a hardware execution unit of the hardware processor by:
receiving a vector element multiplicand and vector element multiplier expressed in a first base system;
converting said vector element multiplicand and vector element multiplier into a second lower base system to form a converted vector element multiplicand and a converted vector element multiplier;
multiplying said converted vector element multiplicand and said converted vector element multiplier to form a multiplication result;
accumulating in a register a portion of said multiplication result with a portion of a result of a prior multiplication of operands expressed in said second lower base system; and
converting contents of said register into said first base system.
2. The method of claim 1 wherein said first base system corresponds to a maximum digit size of 64 bits.
3. The method of claim 2 wherein said second lower base system corresponds to a maximum digit size of 52 bits.
4. The method of claim 1 wherein said contents of said register include a digit that is larger than said second lower base system's largest digit.
5. The method of claim 1 wherein the executing further comprises iteratively performing multiplication and accumulation sequences to effect a complete multiplication of two vectors, and said iterative multiplication and accumulation sequences include a broadcast operation that instantiates one element of a multiplier across each of multiple elements of a vector.
6. The method of claim 5 wherein said iterative multiplication and accumulation sequences include a shift operation that shifts elements of a multiplicand to a neighboring vector element location.
7. A hardware processor comprising:
a hardware decoder to decode a single instruction; and
a hardware execution unit to execute the single instruction to:
receive a vector element multiplicand and vector element multiplier expressed in a first base system;
convert said vector element multiplicand and vector element multiplier into a second lower base system to form a converted vector element multiplicand and a converted vector element multiplier;
multiply said converted vector element multiplicand and said converted vector element multiplier to form a multiplication result;
accumulate in a register a portion of said multiplication result with a portion of a result of a prior multiplication of operands expressed in said second lower base system; and
convert contents of said register into said first base system.
8. The hardware processor of claim 7 wherein said first base system corresponds to a maximum digit size of 64 bits.
9. The hardware processor of claim 8 wherein said second lower base system corresponds to a maximum digit size of 52 bits.
10. The hardware processor of claim 7 wherein said contents of said register include a digit that is larger than said second lower base system's largest digit.
11. The hardware processor of claim 7 wherein said hardware execution unit is to execute the single instruction by iteratively performing multiplication and accumulation sequences to effect a complete multiplication of two vectors and said iterative multiplication and accumulation sequences include a broadcast operation that instantiates one element of a multiplier across each of multiple elements of a vector.
12. The hardware processor of claim 11 wherein said iterative multiplication and accumulation sequences include a shift operation that shifts elements of a multiplicand to a neighboring vector element location.