IP Library Patent Application 13538577
Patent Application
App. No. 13/538,577

SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH A CURRENT CARRYING REGION AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF

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Patent No.
US None
App. No.
13/538,577
Abstract

Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a current carrying region (e.g., a source region of the first conductivity type and/or a drain region of the second conductivity type), and the resistor circuit is connected between the isolation structure and the current carrying region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).

Claims (84)

1 . A semiconductor device, comprising:

a semiconductor substrate having a first conductivity type and a top substrate surface;

a buried layer below the top substrate surface, wherein the buried layer has a second conductivity type that is different from the first conductivity type;

a sinker region between the top substrate surface and the buried layer, wherein the sinker region has the second conductivity type, and an isolation structure is formed by the sinker region and the buried layer;

an active device in the semiconductor substrate within a portion of the substrate contained by the isolation structure, wherein the active device includes a current carrying region selected from a source region and a drain region; and

a resistor circuit connected between the isolation structure and the current carrying region.

2 . The semiconductor device of claim 1 , wherein the resistor circuit comprises:

a polycrystalline silicon resistor.

3 . The semiconductor device of claim 1 , wherein the resistor circuit comprises:

a first resistive network; and

a Schottky diode coupled to the first resistive network, wherein the Schottky diode is formed from a Schottky contact coupled with the isolation region.

4 . The semiconductor device of claim 3 , wherein:

the Schottky diode is coupled to the first resistive network in series.

5 . The semiconductor device of claim 3 , wherein:

the Schottky diode is coupled to the first resistive network in parallel.

6 . The semiconductor device of claim 5 , wherein the resistor circuit further comprises:

a second resistive network coupled to the Schottky diode in series.

7 . The semiconductor device of claim 3 , wherein the resistor circuit further comprises:

a PN junction diode coupled to the Schottky diode in parallel.

8 . The semiconductor device of claim 1 , wherein the resistor circuit comprises:

a first resistive network; and

a PN junction diode coupled to the first resistive network.

9 . The semiconductor device of claim 8 , wherein:

the PN junction diode is coupled to the first resistive network in series.

10 . The semiconductor device of claim 8 , wherein:

the PN junction diode is coupled to the first resistive network in parallel.

11 . The semiconductor device of claim 10 , wherein the resistor circuit further comprises:

a second resistive network coupled to the PN junction diode in series.

12 . The semiconductor device of claim 8 , further comprising:

a further region of the first conductivity type extending into the sinker region, wherein the PN junction diode is formed between the further region and the sinker region.

13 . The semiconductor device of claim 8 , wherein the PN junction diode comprises a polycrystalline silicon diode.

14 . The semiconductor device of claim 1 , wherein the current carrying region is a drain region of the active device, and wherein the drain region is of the second conductivity type.

15 . The semiconductor device of claim 14 , wherein the active device comprises:

a drift region of the second conductivity type within a central portion of the active area and extending from the top substrate surface into the semiconductor substrate;

the drain region extending into the drift region from the top substrate surface;

a body region of the first conductivity type extending from the top substrate surface into the semiconductor substrate between the drift region and the isolation structure;

a source region of the second conductivity type extending into the body region from the top substrate surface; and

a body contact region of the first conductivity type within the body region and extending from the top substrate surface into the semiconductor substrate between the source region and the isolation structure.

16 . The semiconductor device of claim 1 , wherein the current carrying region is a source region of the active device, wherein the source region is of the first conductivity type.

17 . The semiconductor device of claim 16 , wherein the active device comprises:

a drift region of the first conductivity type within a central portion of the active area and extending from the top substrate surface into the semiconductor substrate;

a drain region of the first conductivity type extending into the drift region from the top substrate surface;

a body region of the second conductivity type extending from the top substrate surface into the semiconductor substrate between the drift region and the isolation structure; and

the source region extending into the body region from the top substrate surface.

18 . A driver circuit comprising:

a first laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) formed on a semiconductor substrate having a first conductivity type and a top substrate surface, wherein the first LDMOSFET includes

a buried layer below the top substrate surface, wherein the buried layer has a second conductivity type that is different from the first conductivity type,

a sinker region between the top substrate surface and the buried layer, wherein the sinker region has the second conductivity type, and an isolation structure is formed by the sinker region and the buried layer,

an active device in a portion of the semiconductor substrate contained by the isolation structure, wherein the active device includes a current carrying region; and

a resistor circuit connected between the isolation structure and the current carrying region.

19 . The driver circuit of claim 18 , wherein the resistor circuit comprises:

a polycrystalline silicon resistor.

20 . The driver circuit of claim 18 , wherein the resistor circuit comprises:

a first resistive network; and

a Schottky diode coupled to the first resistive network, wherein the Schottky diode is formed from a Schottky contact coupled with the isolation region.

21 . The driver circuit of claim 20 , wherein the Schottky diode is coupled to the first resistive network in parallel, and the resistor circuit further comprises:

a second resistive network coupled to the Schottky diode in series.

22 . The driver circuit of claim 18 , wherein the resistor circuit comprises:

a first resistive network; and

a PN junction diode coupled to the resistive network.

23 . The driver circuit of claim 22 , further comprising:

a further region of the first conductivity type extending into the sinker region, wherein the PN junction diode is formed between the further region and the sinker region.

24 . The driver circuit of claim 22 , wherein the PN junction diode comprises a polycrystalline silicon diode.

25 . The driver circuit of claim 22 , wherein the PN junction diode is coupled to the first resistive network in parallel, and the resistor circuit further comprises:

a second resistive network coupled to the PN junction diode in series.

26 . A method for forming a semiconductor device, the method comprising the steps of:

forming a buried layer below a top substrate surface of a semiconductor substrate having a first conductivity type, wherein the buried layer has a second conductivity type that is different from the first conductivity type;

forming a sinker region between the top substrate surface and the buried layer, wherein the sinker region has the second conductivity type, and an isolation structure is formed by the sinker region and the buried layer;

forming an active device in a portion of the semiconductor substrate contained by the isolation structure, wherein the active device includes a current carrying region; and

forming a resistor circuit connected between the isolation structure and the current carrying region.

27 . The method of claim 26 , wherein forming the resistor circuit comprises:

forming and interconnecting a polycrystalline silicon resistor as part of the resistor circuit.

28 . The method of claim 26 , wherein the resistor circuit includes a resistive network and a Schottky diode, and forming the resistor circuit comprises:

forming the resistive network;

forming the Schottky diode, wherein the Schottky diode includes a Schottky contact coupled with the isolation region; and

coupling the resistive network to the Schottky contact.

29 . The method of claim 26 , wherein the resistor circuit includes a resistive network and a PN junction diode, and forming the resistor circuit comprises:

forming the resistive network;

forming a further region of the first conductivity type extending into the sinker region, wherein the PN junction diode is formed between the further region and the sinker region; and

coupling the resistive network to the further region.

30 . The method of claim 26 , wherein the resistor circuit includes a resistive network and a PN junction diode, and forming the resistor circuit comprises:

forming the resistive network;

forming the PN junction diode as a polycrystalline silicon diode; and

coupling the resistive network to the polycrystalline silicon diode.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0535 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0555 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0575 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030258/0501 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030258/0479 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 030256/0706 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2012
From: BODE, HUBERT M.; CHEN, WEIZE; DE SOUZA, RICHARD J.; PARRIS, PATRICE M.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029235/0474 →