Method and system to dynamically power-down a block of a pattern-recognition processor
A device includes a pattern-recognition processor. The pattern recognition processor includes blocks, such that each of the blocks include a plurality of feature cells configured to analyze at least a portion of data to be analyzed and to selectively provide a result of the analysis. The pattern recognition processor also includes block deactivation logic configured to dynamically power-down the block.
1. A device, comprising:
a pattern-recognition processor comprising:
blocks, each of the blocks comprising:
a plurality of feature cells configured to analyze at least a portion of data to be analyzed and to selectively provide a result of the analysis; and
block deactivation logic configured to determine whether any of the feature cells of the block are active and to dynamically power-down the block when the block deactivation logic determines that none of the feature cells of the block are active, wherein an activation-routing matrix selectively activates and deactivates the feature cells based on search terms in a search criterion.
2. The device of claim 1 , wherein the block deactivation logic is configured to receive an indication of whether any of the plurality of feature cells of the block are active.
3. The device of claim 2 , wherein the block deactivation logic is configured to dynamically power-down the block based at least in part on the indication of whether any of the plurality of feature cells are active.
4. The device of claim 1 , wherein the block deactivation logic comprises a memory cell configured to receive an indication of whether any of the plurality of feature cells of the block are active.
5. The device of claim 4 , wherein the block deactivation logic is configured to dynamically power-down the block based at least in part on a value stored in the memory cell.
6. The device of claim 1 , wherein the block deactivation logic circuit comprises a plurality of AND gates each having an output terminal coupled to a respective local input conductor, wherein each respective local input conductor is coupled to one of the blocks.
7. The device of claim 6 , wherein the plurality of AND gates each have an input terminal coupled to a respective global input conductor, wherein each respective global input conductor is coupled to at least two of the blocks.
8. The device of claim 6 , wherein the block deactivation logic circuit comprises an OR gate, wherein the plurality of AND gates each have an input terminal coupled to an output terminal of the OR gate.
9. The device of claim 8 , wherein each of the blocks comprise a detection cell, wherein the OR gate has an input terminal coupled to the detection cell.
10. The device of claim 9 , wherein the detection cell is configured to output a value indicative of whether one of the plurality of feature cells is active.
11. The device of claim 1 , wherein the activation-routing matrix is coupled to the block deactivation logic, wherein the activation-routing matrix is configured to transmit an indication of whether any of the plurality of feature cells of the block are active.
12. The device of claim 11 , wherein the block deactivation logic is configured to dynamically power-down the block based at least in part on the indication of whether any of the plurality of feature cells are active.
13. A pattern-recognition processor, comprising:
a first block of first feature cells configured to analyze at least a portion of data to be analyzed and to provide a result of the analysis;
a second block of second feature cells configured to analyze at least a second portion of data to be analyzed and to provide a second result of the analysis; and
block deactivation logic configured to determine whether any of the feature cells of the first block are active and to dynamically power-down the first block when the block deactivation logic determines that none of the feature cells of the block are active, wherein an activation-routing matrix selectively activates and deactivates the first feature cells and the second feature cells based on search terms in a search criterion.
14. The pattern-recognition processor of claim 13 , wherein the activation-routing matrix is coupled to the block deactivation logic, wherein the activation-routing matrix is configured to transmit an indication of whether any of the first feature cells of the first block are active.
15. The pattern-recognition processor of claim 14 , wherein the block deactivation logic is configured to receive the indication of whether any of the first feature cells of the first block are active and dynamically power-down the first block based at least in part on the indication of whether any of the first feature cells are active.
16. The pattern-recognition processor of claim 15 , wherein the block deactivation logic comprises memory configured to store the indication of whether any of the first feature cells of the first block are active.
17. The pattern-recognition processor of claim 13 , comprising a second block deactivation logic configured to dynamically power-down the second block.
18. The pattern-recognition processor of claim 17 , wherein the activation-routing matrix is coupled to the second block deactivation logic, wherein the activation-routing matrix is configured to transmit an indication of whether any of the second feature cells of the second block are active.
19. The pattern-recognition processor of claim 18 , wherein the second block deactivation logic is configured to receive the indication of whether any of the second feature cells of the second block are active and dynamically power-down the second block based at least in part on the indication of whether any of the second feature cells are active.
20. The pattern-recognition processor of claim 18 , wherein the second block deactivation logic comprises memory configured to store the indication of whether any of the second feature cells of the second block are active.
21. A method, comprising:
receiving a signal indicative of a data stream to be searched along a global conductor coupled to a first block of first feature cells and a second block of second feature cells;
determining via block deactivation logic if any of the feature cells in the first block are active; and
transmitting a block deactivation signal from the block deactivation logic to power-down the first block if none of the first feature cells are active, wherein an activation-routing matrix selectively activates and deactivates the first feature cells and the second feature cells based on search terms in a search criterion.
22. The method of claim 21 , wherein determining whether any of the first feature cells in the first block are active comprises outputting a signal from an OR gate coupled to each of the first feature cells.
23. The method of claim 21 , wherein determining whether any of the first feature cells in the first block are active comprises outputting a value stored by a memory cell in the block deactivation logic, wherein the value is indicative of whether any of the first feature cells in the first block are active.
24. The method of claim 21 , comprising:
determining via the block deactivation logic if any of the feature cells in the second block are active; and
transmitting a second block deactivation signal from the block deactivation logic to power-down the second block if none of the second feature cells are active.
25. The method of claim 21 , comprising searching the data stream via the first block or the second block according to search criteria.