Apparatus and method for rounded ONO formation in a flash memory device

1. A memory device, comprising:

a semiconductor layer, including a source/drain region;

an isolation region;

a first insulator disposed above said source/drain region;

a charge trapping layer comprising nitride disposed above said first insulator, wherein said charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein tops of said first and second tips are above a top surface of said bulk portion and form obtuse angles between said top surface of said bulk portion and said tops of said first and second tips;

a second insulator disposed above said charge trapping layer; and

a polysilicon gate structure disposed above said second insulator,

wherein said source/drain region comprises a top surface that is rounded across a width of the source/drain region.

2. The memory device of claim 1 , wherein said polysilicon gate structure includes an obtuse bottom profile including first and second corners corresponding to said first and second tips, wherein said corners are rounded.

3. The memory device of claim 1 , wherein said angle ranges between 120 to 125 degrees.

4. The memory device of claim 1 , wherein said first and second tips extend beyond said source/drain region.

5. The memory device of claim 1 , wherein said top surface is continuously rounded to provide a uniformly rounded shape across the width of said source/drain region.

6. The memory device of claim 5 , wherein said first insulator, said charge trapping layer, said second insulator and said polysilicon gate structure are rounded in conformance with the top surface of the source/drain region to increase a width of a channel in the memory device.

7. The memory device of claim 6 , wherein a width of said polysilicon gate structure is wider than the width of the source/drain region.