Transistor device
To provide a transistor device, which is composed of a compound semiconductor, having a multilayer structure in which a high electron mobility transistor (HEMT) and a heterojunction bipolar transistor (HBT) are overlapped on the same substrate and epitaxial-grown thereon, wherein a band gap energy of an indium gallium phosphide layer (InGaP) included in an epitaxial layer, is set to 1.91 eV or more.
1. A transistor device, having a multilayer structure in which a high electron mobility transistor and a heterojunction bipolar transistor, which are composed of a compound semiconductor, are overlapped on the same substrate and epitaxial-grown thereon,
wherein
the multilayer structure contains an In (1-y) Ga y P layer (0.515≦y<1) as an epitaxial layer, and
a band gap energy of the In (1-y) Ga y P layer (0.515≦y<1) is set to 1.91 eV or more.
2. The transistor device according to claim 1 , wherein the In (1-y) Ga y P layer is a separation layer for separating the high electron mobility transistor from the heterojunction bipolar transistor.
3. The transistor device according to claim 1 , wherein the In (1-y) Ga y P layer is an emitter layer of the heterojunction bipolar transistor.
4. The transistor device according to claim 1 , wherein the In (1-y) Ga y P layer is a separation layer for separating the high electron mobility transistor from the heterojunction bipolar transistor, and an emitter layer of the heterojunction bipolar transistor.
5. The transistor device according to claim 1 , wherein the compound semiconductor is one or more compounds selected from a group consisting of GaAs, AlGaAs, InGaAs, InGaP, and InAlGaP.
6. The transistor device according to claim 2 , wherein the compound semiconductor is one or more compounds selected from a group consisting of GaAs, AlGaAs, InGaAs, InGaP, and InAlGaP.
7. The transistor device according to claim 3 , wherein the compound semiconductor is one or more compounds selected from a group consisting of GaAs, AlGaAs, InGaAs, InGaP, and InAlGaP.
8. The transistor device according to claim 4 , wherein the compound semiconductor is one or more compounds selected from a group consisting of GaAs, AlGaAs, InGaAs, InGaP, and InAlGaP.
9. The transistor device according to claim 5 , wherein the multilayer structure includes a layer doped with n-type impurities as the epitaxial layer, and the n-type impurities are one or more elements selected from a group consisting of Si, Sn, S, Se, and Te.
10. The transistor device according to claim 6 , wherein the multilayer structure includes a layer doped with n-type impurities as the epitaxial layer, and the n-type impurities are one or more elements selected from a group consisting of Si, Sn, S, Se, and Te.
11. The transistor device according to claim 7 , wherein the multilayer structure includes a layer doped with n-type impurities as the epitaxial layer, and the n-type impurities are one or more elements selected from a group consisting of Si, Sn, S, Se, and Te.
12. The transistor device according to claim 8 , wherein the multilayer structure includes a layer doped with n-type impurities as the epitaxial layer, and the n-type impurities are one or more elements selected from a group consisting of Si, Sn, S, Se, and Te.
13. The transistor device according to claim 9 , wherein the multilayer structure includes a layer doped with a p-type impurity as the epitaxial layer, and the P-type impurity is C (carbon).
14. The transistor device according to claim 10 , wherein the multilayer structure includes a layer doped with a p-type impurity as the epitaxial layer, and the P-type impurity is C (carbon).
15. The transistor device according to claim 11 , wherein the multilayer structure includes a layer doped with a p-type impurity as the epitaxial layer, and the P-type impurity is C (carbon).
16. The transistor device according to claim 12 , wherein the multilayer structure includes a layer doped with a p-type impurity as the epitaxial layer, and the P-type impurity is C (carbon).
17. The transistor device according to claim 5 , wherein the multilayer structure further includes a GaAs layer as the epitaxial layer and a lattice mismatch degree between the In (1-y) Ga y P layer and the GaAs layer is within ±500 s in an X-ray analysis measurement.
18. The transistor device according to claim 6 , wherein the multilayer structure further includes a GaAs layer as the epitaxial layer and a lattice mismatch degree between the In (1-y) Ga y P layer and the GaAs layer is within ±500 s in an X-ray analysis measurement.
19. The transistor device according to claim 7 , wherein the multilayer structure further includes a GaAs layer as the epitaxial layer and a lattice mismatch degree between the In (1-y) Ga y P layer and the GaAs layer is within ±500 s in an X-ray analysis measurement.
20. A method of manufacturing a transistor device, comprising:
forming a high electron mobile transistor composed of a compound semiconductor on a substrate;
forming an In (1-y) Ga y P layer (0.515≦y<1) on the high electron mobile transistor at a temperature of allowing a band gap energy to be set to 1.91 eV or more; and
forming a hetero bipolar transistor composed of the compound semiconductor on the In (1-y) Ga y P layer.