Prediction of circuit performance variations due to device mismatch
View Patent ↗Aspects of the invention relate to techniques for predicting circuit performance variations due to device mismatch. Circuit simulation is performed to generate circuit simulation results based on a circuit description and information of circuit element parameters. Based on the simulation results, sensitivity information for the circuit design and current/charge deviations caused by individual circuit element parameter variations may be computed. Based on the sensitivity information and the current/charge deviations, steady-state mismatch effect information is determined. The determination may comprise first computing output parameter deviations caused by the individual variations of the circuit element parameters and then computing a total output parameter deviation based on the output parameter deviations.
1. One or more processor-readable storage media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:
receiving a circuit description of a circuit design that comprises circuit elements and information of circuit element parameters for the circuit elements;
performing circuit simulation using the circuit description and the information of circuit element parameters to generate circuit simulation results;
computing sensitivity information based on the circuit simulation results;
computing, based on the circuit simulation results, current/charge deviations caused by individual circuit element parameter variations;
determining steady-state mismatch effect information based on the sensitivity information and the current/charge deviations; and
outputting the steady-state mismatch effect information.
2. The one or more processor-readable storage media recited in claim 1 , wherein the circuit description is a transistor-level netlist.
3. The one or more processor-readable storage media recited in claim 1 , wherein the circuit simulation employs a harmonic balance method.
4. The one or more processor-readable storage media recited in claim 1 , wherein the circuit simulation results comprise nominal current/charge values for the circuit elements, and the current/charge deviations are computed with respect to the nominal current/charge values.
5. The one or more processor-readable storage media recited in claim 1 , wherein the sensitivity information comprises adjoint sensitivity information.
6. The one or more processor-readable storage media recited in claim 1 , wherein the outputting comprises storing the steady-state mismatch effect information in computer memory or storage.
7. The one or more processor-readable storage media recited in claim 1 , wherein the determining steady-state mismatch effect information comprises:
computing output parameter deviations caused by the individual variations of the circuit element parameters based on the sensitivity information and the current/charge deviations; and
computing a total output parameter deviation based on the output parameter deviations.
8. The one or more processor-readable storage media recited in claim 7 , wherein the computing a total output parameter deviation comprises:
calculating square root of the sum of the squares of the output parameter deviations.
9. The one or more processor-readable storage media recited in claim 1 , wherein the information of circuit element parameters comprises nominal circuit element parameter values.
10. A method of mismatch analysis, comprising:
with a computer,
receiving a circuit description of a circuit design that comprises circuit elements and information of circuit element parameters for the circuit elements;
performing circuit simulation using the circuit description and the information of circuit element parameters to generate circuit simulation results;
computing sensitivity information based on the circuit simulation results;
computing, based on the circuit simulation results, current/charge deviations caused by individual circuit element parameter variations;
determining steady-state mismatch effect information based on the sensitivity information and the current/charge deviations; and
outputting the steady-state mismatch effect information.
11. The method recited in claim 10 , wherein the circuit description is a transistor-level netlist.
12. The method recited in claim 10 , wherein the circuit simulation employs a harmonic balance method.
13. The method recited in claim 10 , wherein the circuit simulation results comprise nominal current/charge values for the circuit elements, and the current/charge deviations are computed with respect to the nominal current/charge values.
14. The method recited in claim 10 , wherein the sensitivity information comprises adjoint sensitivity information.
15. The method recited in claim 10 , wherein the outputting comprises storing the steady-state mismatch effect information in computer memory or storage.
16. The method recited in claim 10 , wherein the determining steady-state mismatch effect information comprises:
computing output parameter deviations caused by the individual variations of the circuit element parameters based on the sensitivity information and the current/charge deviations; and
computing a total output parameter deviation based on the output parameter deviations.
17. The method recited in claim 16 , wherein the computing a total output parameter deviation comprises:
calculating square root of the sum of the squares of the output parameter deviations.
18. The method recited in claim 10 , wherein the information of circuit element parameters comprises nominal circuit element parameter values.