System for testing error detection circuits
View Patent ↗A system for testing an error detection circuit includes a fault injection unit for operating the error detection circuit in a fault injection mode. A fault is inserted in either of a primary or a redundant processor. Output signals generated by the primary and redundant processors are compared and checked for a mismatch and the error detection circuit outputs a test signal based on the comparison result.
1. A system for testing an error detection circuit by injecting a fault into the error detection circuit, wherein the error detection circuit receives first and second output signals generated by first and second processors, the system comprising:
an inverter for receiving an input signal and generating an inverted input signal;
a first logic gate for receiving test mode and fault injection mode signals and generating an input selection signal based on the test mode and fault injection mode signals; and
a mux having a first input terminal that receives one of the input signal and a scan input signal, a second input terminal connected to the inverter and receiving the inverted input signal, a select input terminal connected to the first logic gate and receiving the input selection signal, and an output terminal for providing one of the input signal, scan input signal and inverted input signal,
wherein the mux output terminal is connected to the second processor and the second processor generates the second output signal based on one of the input and inverted input signals, and the first processor generates the first output signal based on the input signal, and
wherein the error detection circuit receives and compares the first and second output signals from the first and second processors, and generates an error signal based on a result of the comparison.
2. The system of claim 1 , further comprising a second logic gate having a first input terminal connected to an output terminal of the first logic gate for receiving the input selection signal and a second input terminal for receiving a scan mode enable signal, wherein the second logic gate generates a mode selection signal.
3. The system of claim 2 , further comprising:
a flip-flop having a data input terminal for receiving the input signal, a test input terminal connected to the output terminal of the mux for receiving the one of the scan input and inverted input signals, a scan enable terminal connected to the second logic gate for receiving the mode selection signal, and an output terminal for providing an intermediate signal to the second processor.
4. The system of claim 3 , wherein the second processor generates the second output signal based on the intermediate signal.
5. The system of claim 1 , wherein the error detection circuit is a redundancy checker circuit.
6. The system of claim 5 , wherein the redundancy checker circuit is a part of an automobile safety device, wherein the redundancy checker circuit is tested during a functional operation of the automobile safety device.
7. The system of claim 1 , wherein the test mode signal is a join test action group (JTAG) signal.
8. The system of claim 1 , wherein the first processor is a primary processor and the second processor is a redundant processor.
9. The system of claim 1 , wherein the inverter comprises a NOT gate and the first logic gate comprises an AND gate.
10. A system for testing an error detection circuit by injecting a fault therein, wherein the error detection circuit receives first and second output signals generated by first and second processors, the error detection circuit comprising:
a NOT gate for receiving an input signal and generating an inverted input signal;
an AND gate for receiving test mode and fault injection mode signals and generating an input selection signal;
a mux having a first input terminal connected to the NOT gate for receiving the inverted input signal, a second input terminal for receiving a scan input signal, a select input terminal connected to the AND gate for receiving the input selection signal, and an output terminal for providing one of the inverted input and scan input signals;
an OR gate having a first input terminal connected to the AND gate for receiving the input selection signal, a second input terminal for receiving a scan mode enable signal, and an output terminal for providing a mode selection signal; and
a flip-flop having a data input terminal for receiving the input signal, a test input terminal connected to the output terminal of the mux for receiving the selected one of the scan input and inverted input signals, a scan enable terminal connected to the OR gate for receiving the mode selection signal, a clock input terminal for receiving a clock input signal, and an output terminal for providing an intermediate signal to the second processor,
wherein the second processor generates the second output signal based on the intermediate signal and the first processor generates the first output signal based on the input signal, and
wherein the error detection circuit generates an error signal when the first and second output signals are not identical.
11. The system of claim 10 , wherein the error detection circuit is a redundancy checker circuit.
12. The system of claim 11 , wherein the redundancy checker circuit is a part of an automobile safety device, wherein the system tests the redundancy checker circuit during a functional operation of the automobile safety device.
13. The system of claim 10 , wherein the test mode signal is a join test action group (JTAG) signal.
14. The system of claim 10 , wherein the first and second processors are at least one of primary and redundant processors.
15. A system for testing an error detection circuit connected to first and second processors, the system comprising:
an inverter for receiving an input signal and generating an inverted input signal;
a first logic gate for receiving test mode and fault injection mode signals and generating an input selection signal;
a mux having a first input terminal for receiving the input signal, a second input terminal connected to the inverter for receiving the inverted input signal, a select input terminal connected to the first logic gate for receiving the input selection signal, and an output terminal for providing one of the input and inverted input signals based on the input selection signal;
a flip-flop having a data input terminal connected to the output terminal of the mux for receiving the one of the input and inverted input signals, a test input terminal for receiving a scan input signal, a scan enable terminal for receiving a scan mode enable signal, and a clock input terminal for receiving a clock input signal, wherein the flip-flop outputs an intermediate signal to the second processor,
wherein the first processor generates a first output signal based on the input signal and the second processor generates a second output signal based on the intermediate signal; and
wherein the error detection circuit receives and compares the first and second output signals and generates an error signal when the first and second output signals are not identical.
16. The system of claim 15 , wherein the first logic gate comprises an AND gate.
17. The system of claim 15 , wherein the first and second processors are at least one of primary and redundant processors.