IP Library Granted Patent US 8,853,553
Granted Patent B2
US 8,853,553 · App. 13/548,234 · Granted Oct 7, 2014

Ball grid array (BGA) and printed circuit board (PCB) via pattern to reduce differential mode crosstalk between transmit and receive differential signal pairs

Inventors: Mark A. Hinton (Fort Collins, CO); Minh V. Quach (San Jose, CA); Regee Petaja (Loveland, CO)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
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Quick Facts
Patent No.
US 8,853,553
App. No.
13/548,234
Granted
Oct 7, 2014
Kind
B2
Abstract

A ball grid array (BGA) and via pattern includes a printed circuit board (PCB) having a surface on which a plurality of regions are formed and a transmit (TX) and receive (RX) cluster comprising a transmit differential signal pair and a receive differential signal pair formed using at least a portion of the plurality of regions on the surface of the PCB, the transmit differential signal pair and the receive differential signal pair comprising nodes arranged in a diagonal orientation in which each node of the receive differential signal pair is equidistant from each node of the transmit differential signal pair.

Claims (26)

1. A ball grid array (BGA) and via pattern, comprising:

a printed circuit board (PCB) having a surface on which a plurality of regions are formed; and

a transmit (TX) and receive (RX) cluster comprising a transmit differential signal pair and a receive differential signal pair formed using at least a portion of the plurality of regions on the surface of the PCB, the transmit differential signal pair comprising two nodes arranged in a diagonal orientation and the receive differential signal pair comprising two nodes arranged in a diagonal orientation, wherein each node of the receive differential signal pair is equidistant from each node of the transmit differential signal pair.

2. The ball grid array (BGA) and via pattern of claim 1 , wherein a plurality of TX/RX clusters are separated by at least one ground region.

3. The ball grid array (BGA) and via pattern of claim 1 , wherein each node of the differential signal pair is connected to a solder ball.

4. The ball grid array (BGA) and via pattern of claim 1 , wherein each node of the differential signal pair comprises a via.

5. The ball grid array (BGA) and via pattern of claim 1 , wherein each node of the receive differential signal pair being equidistant from each node of the transmit differential signal pair results in a net differential mode crosstalk of zero imparted to the receive differential signal pair.

6. The ball grid array (BGA) and via pattern of claim 5 , wherein crosstalk appearing at each node of the receive differential signal pair comprises crosstalk from each node of the transmit differential signal pair.

7. The ball grid array (BGA) and via pattern of claim 1 , wherein a plurality of TX/RX clusters are separated from core logic functional connections by at least one ground region.

8. The ball grid array (BGA) and via pattern of claim 1 , wherein a plurality of TX/RX clusters are arranged around a periphery of a quadrant of the PCB.

9. A method for communicating using a ball grid array (BGA) and via pattern, comprising:

providing a printed circuit board (PCB) to have a surface on which a plurality of regions are formed; and

providing a transmit (TX) and receive (RX) cluster comprising a transmit differential signal pair and a receive differential signal pair using at least a portion of the plurality of regions on the surface of the PCB, the transmit differential signal pair comprising two nodes arranged in a diagonal orientation and the receive differential signal pair comprising two nodes arranged in a diagonal orientation, wherein each node of the receive differential signal pair is equidistant from each node of the transmit differential signal pair.

10. The method of claim 9 , further comprising separating a plurality of TX/RX clusters by at least one ground region.

11. The method of claim 9 , further comprising connecting each node of the differential signal pair to a solder ball.

12. The method of claim 9 , wherein each node of the differential signal pair comprises a via.

13. The method of claim 12 , wherein each node of the receive differential signal pair being equidistant from each node of the transmit differential signal pair results in a net differential mode crosstalk of zero imparted to the receive differential signal pair.

14. A ball grid array (BGA) and via pattern for a printed circuit board (PCB), comprising:

a printed circuit board (PCB) having a surface on which a plurality of regions are formed; and

a transmit (TX) and receive (RX) cluster comprising a transmit differential signal pair and a receive differential signal pair formed using at least a portion of the plurality of regions on the surface of the PCB, the transmit differential signal pair comprising two nodes arranged in a diagonal orientation and the receive differential signal pair comprising two nodes arranged in a diagonal orientation, wherein each node of the receive differential signal pair is equidistant from each node of the transmit differential signal pair, wherein a plurality of TX/RX clusters are separated by at least one ground region.

15. The ball grid array (BGA) and via pattern for a printed circuit board (PCB) of claim 14 , wherein each node of the differential signal pair is connected to a solder ball.

16. The ball grid array (BGA) and via pattern for a printed circuit board (PCB) of claim 14 , wherein each node of the differential signal pair comprises a via.

17. The ball grid array (BGA) and via pattern for a printed circuit board (PCB) of claim 14 , wherein each node of the receive differential signal pair being equidistant from each node of the transmit differential signal pair results in a net differential mode crosstalk of zero imparted to the receive differential signal pair.

18. The ball grid array (BGA) and via pattern for a printed circuit board (PCB) of claim 17 , wherein crosstalk appearing at each node of the receive differential signal pair comprises crosstalk from each node of the transmit differential signal pair.

19. The ball grid array (BGA) and via pattern for a printed circuit board (PCB) of claim 14 , wherein a plurality of TX/RX clusters are separated from core logic functional connections by at least one ground region.

20. The ball grid array (BGA) and via pattern for a printed circuit board (PCB) of claim 14 , wherein a plurality of TX/RX clusters are arranged around a periphery of a quadrant of the PCB.

Assignments (11)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030370/0008 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2012
From: HINTON, MARK A.; QUACH, MINH V.; PETAJA, REGEE
To: AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE. LTD.
Reel/Frame 028541/0225 →
Continuity (1)
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