Methods and structures for multiport memory devices
A memory device includes a storage unit formed using a substrate, a true bit line BL 0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.
1. A memory device, comprising:
a storage unit formed using a substrate;
a first true bit line for carrying a bit of data, wherein the first true bit line is coupled to the storage unit and runs laterally over the substrate; and
a first complementary bit line for carrying the bit of data carried by the first true bit line in complementary form,
wherein the first true bit line and the first complementary bit line are adjacent to each other and vertically stacked one on top of the other above the substrate.
2. The memory device of claim 1 , further comprising a first via stack and a second via stack that are in a line parallel to the first true bit line and the first complementary bit line, wherein the first via stack couples the first true bit line to the storage unit and the second via stack couples the first complementary bit line to the storage unit.
3. The memory device of claim 2 , wherein the storage unit comprises a first pass transistor and a second pass transistor, wherein the first via stack is coupled to the first pass transistor and the second via stack is coupled to the second pass transistor.
4. The memory device of claim 1 , further comprising:
a second true bit line for carrying a bit of data, wherein the second true bit line is coupled to the storage unit and runs parallel to the first true bit line and first complementary bit line; and
a second complementary bit line for carrying the bit of data carried by the second true bit line in complementary form;
wherein the second true bit line and the second complementary bit line are adjacent to each other and vertically stacked above the substrate.
5. The memory device of claim 4 , further comprising:
a third via stack and a fourth via stack that are in line with the first and second via stacks, wherein the third via stack couples the second true bit line to the storage unit and the fourth via stack couples the second complementary bit line to the storage unit.
6. The memory device of claim 5 , wherein the line of the first, second, third, and fourth via stacks is between the first true bit line and the second true bit line.
7. The memory device of claim 6 , wherein:
the first, second, third, and fourth via stacks each have a first portion formed from a first metal layer and a second portion formed from a second metal layer formed at a time difference from the first metal layer in which an insulating layer is formed during the time difference;
the first and second bit lines are from the second metal layer and the first and second complementary bit lines are from the first metal layer;
the first portion of the first via stack is connected to the first true bit line by a first connecting portion of the second metal layer;
the first portion of the third via stack is connected to the second true bit line by a second connecting portion of the second metal layer,
the first portion of the second via stack is connected to the first complementary bit line by a first connecting portion of the first metal layer; and
the first portion of the fourth via stack is connected to the second true bit line by a second connecting portion of the first metal layer.
8. The memory device of claim 6 , wherein the storage unit further comprises a third pass transistor and a fourth pass transistor, wherein the third via stack is coupled to the third pass transistor and the fourth via stack is coupled to the fourth pass transistor.
9. The memory device of claim 8 , further comprising a first word line and a second word line running orthogonal to and above the first and second true bit lines and the first and second complementary bit lines, wherein the first word line is coupled to gates of the first and second pass transistors and the second word line is coupled to gates of the third and fourth pass transistors.
10. The memory device of claim 1 , further comprising a word line running orthogonal to and over the first true bit line and the first complementary bit line and coupled to the storage unit.
11. A memory device, comprising:
a static random access memory cell including transistors in a substrate and having a first input/output, a second input/output, and a first control input, wherein the first control input enables the first and second input/outputs and the first input/output is complementary to the second input/output;
a first bit line coupled to the first input/output; and
a second bit line coupled to the second input/output,
wherein:
the first bit line and the second bit line are stacked vertically one on top of the other above a plane of the substrate in which a first insulating layer is over the first bit line and the second bit line is over the insulating layer.
12. The memory device of claim 11 wherein the static random access memory cell has a third input/output, a fourth input/output, and a second control input, wherein the second control input enables the third and fourth input/outputs and the third input/output is complementary to the fourth input/output, further comprising:
a third bit line coupled to the third input/output; and
a fourth bit line coupled to the fourth input/output,
wherein the third bit line and the fourth bit line are stacked vertically above the plane of the substrate in which a second insulating layer is over the third bit line and the fourth bit line is over the insulating layer.
13. The memory device of claim 12 , wherein the first and second bit lines run in a first line, the third and fourth bit lines run in a second line parallel to the first line, and the first line is laterally spaced from the second line, further comprising
a first via stack, a second via stack, a third via stack and a fourth via stack that run in a third line parallel to and between the first and second lines,
wherein:
the first via stack is coupled to the first input/output and the first bit line;
the second via stack is coupled to the second input/output and the second bit line;
the third via stack is coupled to the third input/output and the third bit line; and
the fourth via stack is coupled to the fourth input/output and the fourth bit line.