Classifying processor testcases
View Patent ↗Embodiments of a testcase checker system are disclosed herein. Embodiments of a testcase checker system may include an instruction set simulator configured to simulate execution of instructions of a testcase on a microprocessor using a reference model associated with an architecture of the microprocessor. The instruction set simulator may generate logging data associated with the each instruction based on the simulated execution of that instruction. The testcase checker system may also include checker module comprising a set of rules. Each of these rules may be associated with a boundedly undefined condition. The checker module is configured to receive the logging data associated with an instruction from the instruction set simulator and process the logging data based on the rules to determine if any of the rules are violated.
1. A testcase checker system, comprising:
a processor; and
a computer readable medium, the computer readable medium comprising instructions to be executed by the processor, the instructions include:
an instruction set simulator configured to simulate execution of each instruction of a sequence of instructions of a testcase on a microprocessor, wherein simulating the execution of each instruction includes using a reference model associated with an architecture of the microprocessor, and to generate logging data associated with each instruction of the sequence of instructions based on the simulated execution of that instruction; and
a checker module comprising a set of rules, wherein each rule is associated with a boundedly undefined condition and the checker module is configured to receive the logging data associated with each instruction from the instruction set simulator and to process the logging data associated with each instruction based on each rule to determine if each rule is violated.
2. The testcase checker system of claim 1 , wherein the checker module is configured to classify a testcase as valid or invalid, wherein the testcase is classified as invalid if any of the set of rules are violated.
3. The testcase checker system of claim 2 , wherein the instruction set simulator is configured to generate logging data associated with the simulated execution of an instruction during a fetch of the instruction, a simulated execution of the instruction and an update to an architectural state of the microprocessor.
4. The testcase checker system of claim 3 , wherein the logging data includes translation data, data on a state change, data on usage of a resource, data on a register state change or a fetch address.
5. The testcase checker system of claim 2 , wherein the set of rules comprise an endian aliasing rule, a context synchronization rule, an implicit branching rule and a cache inhibited aliasing rule.
6. The testcase checker system of claim 2 , wherein the computer readable medium further comprises instructions for a wrapper configured to invoke the instruction set simulator on the testcase.
7. The testcase checker system of claim 2 , wherein the checker module is configured to receive logging data associated with a first instruction of the sequence of instructions from the instruction set simulator and to store the logging data associated with the first instruction based on a first rule, to receive logging data associated with a second instruction of the sequence of instructions that is subsequent to the first instruction and to determine if the first rule is violated based on the stored logging data associated with the first instruction and the logging data associated with the second instruction.
8. A method for testcase classification, comprising:
simulating, by a processor, execution of each instruction of a sequence of instructions of a testcase on a microprocessor, wherein simulating the execution of each instruction includes using a reference model associated with an architecture of the microprocessor;
generating logging data associated with each instruction of the sequence of instructions based on the simulated execution of that instruction; and
processing the logging data associated with each instruction based on each of a set of rules to determine if each rule is violated, wherein each rule is associated with a boundedly undefined condition.
9. The method of claim 8 , further comprising classifying a testcase as valid or invalid, wherein the testcase is classified as invalid if any of the set of rules are violated.
10. The method of claim 9 , wherein the logging data is generated in association with the simulated execution of an instruction during a fetch of the instruction, a simulated execution of the instruction and an update to an architectural state of the microprocessor.
11. The method of claim 10 , wherein the logging data includes translation data, data on a state change, data on usage of a resource, data on a register state change or a fetch address.
12. The method of claim 11 , wherein the set of rules comprise an endian aliasing rule, a context synchronization rule, an implicit branching rule and a cache inhibited aliasing rule.
13. The method of claim 9 , further comprising invoking the instruction set simulator on the testcase with a wrapper.
14. The method of claim 9 , wherein processing the logging data associated with each instruction further comprises storing logging data associated with a first instruction based on a first rule and determining if the first rule is violated based on the stored logging data associated with the first instruction and logging data associated with a second instruction of the sequence of instructions that is subsequent to the first instruction.
15. A non-transitory computer readable medium, the computer readable medium comprising instructions for:
simulating execution of each instruction of a sequence of instructions of a testcase on a microprocessor, wherein simulating the execution of each instruction includes using a reference model associated with an architecture of the microprocessor;
generating logging data associated with each instruction of the sequence of instructions based on the simulated execution of that instruction; and
processing the logging data associated with each instruction based on each of a set of rules to determine if each rule is violated, wherein each rule is associated with a boundedly undefined condition.
16. The non-transitory computer readable medium of claim 15 , further comprising classifying a testcase as valid or invalid, wherein the testcase is classified as invalid if any of the set of rules are violated.
17. The non-transitory computer readable medium of claim 16 , wherein the logging data is generated in association with the simulated execution of an instruction during a fetch of the instruction, a simulated execution of the instruction and an update to an architectural state of the microprocessor.
18. The non-transitory computer readable medium of claim 17 , wherein the logging data includes translation data, data on a state change, data on usage of a resource, data on a register state change or a fetch address.
19. The non-transitory computer readable medium of claim 16 , wherein the set of rules comprise an endian aliasing rule, a context synchronization rule, an implicit branching rule and a cache inhibited aliasing rule.
20. The non-transitory computer readable medium of claim 16 , wherein the computer readable medium further comprises instructions for a wrapper configured to invoke the instruction set simulator on the testcase and wherein processing the logging data associated with each instruction further comprises storing logging data associated with a first instruction based on a first rule and determining if the first rule is violated based on the stored logging data associated with the first instruction and logging data associated with a second instruction of the sequence of instructions that is subsequent to the first instruction.