IP Library Granted Patent US 9,048,210
Granted Patent B2
US 9,048,210 · App. 13/550,032 · Granted Jun 2, 2015

Transistors and methods of manufacturing the same

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Quick Facts
Patent No.
US 9,048,210
App. No.
13/550,032
Granted
Jun 2, 2015
Kind
B2
Abstract

A transistor includes a device portion and a collector layer. The device portion is in a first side of a semiconductor substrate, and includes a gate and an emitter. The collector layer is on a second side of the semiconductor substrate, which is opposite to the first side. The collector layer is an impurity-doped epitaxial layer and has a doping profile with a non-normal distribution.

Claims (25)

1. A method of manufacturing a transistor, the method comprising:

epitaxially growing a collector layer on a first side of a semiconductor substrate;

removing a portion of the semiconductor substrate from a second side of the semiconductor substrate; and

forming a device portion in a surface region of the semiconductor substrate that is exposed by the removing of the portion of the semiconductor substrate from the second side of the semiconductor substrate.

2. The method of claim 1 , further comprising:

doping the collector layer with an impurity during the epitaxially growing of the collector layer.

3. The method of claim 1 , wherein the collector layer has a doping profile with a non-normal distribution.

4. The method of claim 1 , further comprising:

epitaxially growing a buffer layer on the first side of the semiconductor substrate, wherein

the collector layer is epitaxially grown on the buffer layer.

5. The method of claim 4 , further comprising:

doping the buffer layer with an impurity when epitaxially growing the buffer layer.

6. The method of claim 4 , wherein the buffer layer has a doping profile with a non-normal distribution.

7. The method of claim 4 , wherein the buffer layer is a field stop layer.

8. The method of claim 1 , further comprising:

attaching a support substrate to the collector layer before removing the portion of the semiconductor substrate.

9. The method of claim 8 , further comprising:

removing the support substrate after forming the device portion.

10. The method of claim 9 , further comprising:

forming a collector electrode contacting the collector layer after removing the support substrate.

11. The method of claim 1 , wherein the forming of the device portion comprises:

forming a first-conductivity type well region in the surface region of the semiconductor substrate;

forming a second-conductivity type impurity region in the first-conductivity type well region;

forming a gate configured to electrically control a portion of the first-conductivity type well region adjacent to the second-conductivity type impurity region; and

forming an emitter electrode that electrically contacts the first-conductivity type well region and the second-conductivity type impurity region.

Assignments (2)
LICENSE Recorded Jun 23, 2023
From: SAMSUNG ELECTRONICS CO., LTD.
To: INTELLECTUAL KEYSTONE TECHNOLOGY LLC
Reel/Frame 064444/0863 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2012
From: JEONG, HYUNG-SU; SHIN, JAI-KWANG; LEE, NAM-YOUNG; LEE, JI-HOON; CHO, MIN-KWON; CHOI, YONG-CHEOL; CHOI, HYUK-SOON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 028612/0401 →