Semiconductor memory device and method with auxiliary I/O line assist circuit and functionality
View Patent ↗A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.
1. A semiconductor device comprising:
a pair of first data lines transferring complementary signals;
a second data line;
a first circuit coupled with the pair of first data lines to generate a control signal from the complementary signals;
a second circuit driving the second data line from a first potential level to a second potential level in response to the control signal; and
a third circuit driving the second data line from the first potential level to the second potential level in parallel to the second circuit in response to a potential level of the second data line exceeding a prescribed value.
2. The device as claimed in claim 1 , further comprising a memory cell, wherein the complementary signals transmitted by the pair of first data lines is read out from the memory cell.
3. The device as claimed in claim 2 , further comprising a sense amplifier amplifying the complementary signals on the pair of first data lines.
4. The device as claimed in claim 3 , wherein the second data line is a single-ended data line.
5. The device as claimed in claim 2 , wherein the second data line is a single-ended data line.
6. The device as claimed in claim 1 , further comprising a fourth circuit coupled to the second data line to amplify the potential level of the second data line.
7. The device as claimed in claim 6 , wherein the fourth circuit is connected to an end of the second data line, and the third circuit is connected to the other end of the second data line.
8. The device as claimed in claim 6 , wherein the fourth circuit comprises a latch circuit for latching the logic level transmitted through the second data line.
9. The device as claimed in claim 1 , further comprising a fifth circuit operative to precharge the second data line to the first potential level.
10. The device as claimed in claim 9 , wherein the second data line is a single-ended data line.
11. The device as claimed in claim 1 , wherein
the second circuit includes an MIS transistor; and
the second circuit receives the control signal with a gate terminal of the MIS transistor.
12. The device as claimed in claim 11 , wherein one of source and drain terminals of the MIS transistor is connected to the second data line.
13. The device as claimed in claim 11 , wherein the MIS transistor comprises an n-channel MIS transistor.
14. The device as claimed in claim 1 , wherein the second data line is a single-ended data line.
15. A method comprising:
providing complementary signals onto a pair of first data lines;
generating a control signal from the complementary signals;
driving a second data line from a first potential level to a second potential level in response to the control signal; and
supplementing the driving the second data line from the first potential level to the second potential level in response to a potential level of the second data line exceeding a prescribed value.
16. The method as claimed in claim 15 , further comprising reading, before the providing the complementary signals; the complementary signals from a memory cell.
17. The method as claimed in claim 16 , further comprising amplifying, before the generating the control signal, the complementary signals on the pair of first data lines.
18. The method as claimed in claim 15 , further comprising amplifying the potential level of the second data line.
19. The method as claimed in claim 18 , wherein the amplifying the potential level of the second data line is carried out at an end of the second data line, and the supplementing the driving is carried out at the other end of the second data line.
20. The method as claimed in claim 18 , further comprising latching, after the amplifying the potential level of the second data line, the potential level of the second data line.
21. The method as claimed in claim 15 , further comprising precharging, before the driving the second data line, the second data line to the first potential level.
22. The method as claimed in claim 15 , wherein the driving the second data line comprises receiving the control signal with a gate terminal of an MIS transistor.
23. The method as claimed in claim 22 , wherein one of source and drain terminals of the MIS transistor is connected to the second data line.
24. The method as claimed in claim 22 , wherein the MIS transistor comprises an n-channel MIS transistor.