Compound semiconductor device and method of manufacturing the same
An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a first p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a second p-type semiconductor layer formed between the electron supply layer and at least one of the source electrode and the drain electrode. The one of the source electrode and the drain electrode on the second p-type semiconductor layer includes: a first metal film; and a second metal film which contacts the first metal film on the gate electrode side of the first metal film, and a resistance of which is higher than that of the first metal film.
1. A compound semiconductor device comprising:
a substrate;
an electron channel layer and an electron supply layer formed over the substrate;
a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer;
a first p-type semiconductor layer formed between the electron supply layer and the gate electrode; and
a second p-type semiconductor layer formed between the electron supply layer and at least one of the source electrode and the drain electrode,
wherein the one of the source electrode and the drain electrode on the second p-type semiconductor layer comprises:
a first metal film; and
a second metal film which contacts the first metal film on the gate electrode side of the first metal film, and a resistance of which is higher than that of the first metal film.
2. The compound semiconductor device according to claim 1 , wherein a thickness of the second p-type semiconductor layer is 5 nm or smaller.
3. The compound semiconductor device according to claim 1 , wherein the first p-type semiconductor layer and the second p-type semiconductor layer are integral with each other.
4. The compound semiconductor device according to claim 1 , wherein the first p-type semiconductor layer is thicker than the second p-type semiconductor layer.
5. The compound semiconductor device according to claim 1 , wherein each of the first p-type semiconductor layer and the second p-type semiconductor layer is a p-type GaN layer.
6. The compound semiconductor device according to claim 1 , wherein a value of “Sb/Sa” is 0.0065 or more and 0.02 or less, “Sa” representing a contact area between the first metal film and the second p-type semiconductor layer and “Sa” representing a contact area between the second metal film and the second p-type semiconductor layer.
7. The compound semiconductor device according to claim 1 , wherein the first metal film contains one selected from the group consisting of Ir, W, Cu, Ag, Zn, Cr, Al, Ti, Mn, Ta, Si, TaN, TiN, Si 3 N 4 , Ru, ITO (indium tin oxide), NiO, IrO, SrRuO, CoSi 2 , WSi 2 , NiSi, MoSi 2 , TiSi 2 , Al—Si, Al—Cu, and Al—Si—Cu.
8. The compound semiconductor device according to claim 1 , wherein the second metal film contains one selected from the group consisting of Ni, Pd, Au, and Pt.
9. A power supply apparatus comprising
a compound semiconductor device, which comprises:
a substrate;
an electron channel layer and an electron supply layer formed over the substrate;
a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer;
a first p-type semiconductor layer formed between the electron supply layer and the gate electrode; and
a second p-type semiconductor layer formed between the electron supply layer and at least one of the source electrode and the drain electrode,
wherein the one of the source electrode and the drain electrode on the second p-type semiconductor layer comprises:
a first metal film; and
a second metal film which contacts the first metal film on the gate electrode side of the first metal film, and a resistance of which is higher than that of the first metal film.
10. An amplifier comprising
a compound semiconductor device, which comprises:
a substrate;
an electron channel layer and an electron supply layer formed over the substrate;
a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer;
a first p-type semiconductor layer formed between the electron supply layer and the gate electrode; and
a second p-type semiconductor layer formed between the electron supply and at least one of the source electrode and the drain electrode,
wherein the one of the source electrode and the drain electrode on the second p-type semiconductor layer comprises:
a first metal film; and
a second metal film which contacts the first metal film on the gate electrode side of the first metal film, and a resistance of which is higher than that of the first metal film.
11. A method of manufacturing a compound semiconductor device, comprising:
forming an electron channel layer and an electron supply layer over the substrate;
forming a first p-type semiconductor layer and a second p-type semiconductor layer on or above the electron supply layer;
forming a gate electrode, a source electrode and a drain electrode on or above the electron supply layer, wherein
the gate electrode is formed above the first p-type semiconductor layer,
at least one of the source electrode and the drain electrode is formed on the second p-type semiconductor layer, and
the forming the gate electrode, the source electrode and the drain electrode comprises:
forming a first metal film; and
forming a second metal film which contacts the first metal film on the gate electrode side of the first metal film, and a resistance of which is higher than that of the first metal film, the first metal film and the second film being in the one of the source electrode and the drain electrode on the second p-type semiconductor layer.
12. The method of manufacturing a compound semiconductor device according to claim 11 , wherein a thickness of the second p-type semiconductor layer is 5 nm or smaller.
13. The method of manufacturing a compound semiconductor device according to claim 11 , wherein the first p-type semiconductor layer and the second p-type semiconductor layer are integral with each other.
14. The method of manufacturing a compound semiconductor device according to claim 11 , wherein the first p-type semiconductor layer is thicker than the second p-type semiconductor layer.
15. The method of manufacturing a compound semiconductor device according to claim 11 , wherein each of the first p-type semiconductor layer and the second p-type semiconductor layer is a p-type GaN layer.
16. The method of manufacturing a compound semiconductor device according to claim 11 , wherein a value of “Sb/Sa” is 0.0065 or more and 0.02 or less, “Sa” representing a contact area between the first metal film and the second p-type semiconductor layer and “Sa” representing a contact area between the second metal film and the second p-type semiconductor layer.
17. The method of manufacturing a compound semiconductor device according to claim 11 , wherein the first metal film contains one selected from the group consisting of Ir, W, Cu, Ag, Zn, Cr, Al, Ti, Mn, Ta, Si, TaN, TiN, Si 3 N 4 , RU, ITO (indium tin oxide), NiO, IrO, SrRuO, CoSi 2 , WSi 2 , NiSi, MoSi 2 , TiSi 2 , Al—Si, Al—Cu, and Al—Si—Cu.
18. The method of manufacturing a compound semiconductor device according to claim 11 , wherein the second metal film contains one selected from the group consisting of Ni, Pd, Au, and Pt.