IP Library Granted Patent US 8,575,730
Granted Patent B2
US 8,575,730 · App. 13/554,573 · Granted Nov 5, 2013

Semiconductor device

Inventor: Yasutaka Nakashiba (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,575,730
App. No.
13/554,573
Granted
Nov 5, 2013
Kind
B2
Abstract

Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.

Claims (24)

1. A semiconductor device comprising:

an interconnect substrate including a first interconnect; and

a semiconductor chip mounted on the interconnect substrate, the semiconductor chip including:

a substrate;

an interconnect layer provided on a surface of the substrate;

a second interconnect provided in the interconnect layer, the second interconnect formed to have an electric coil-shape; and

an electroconductive pattern formed on the interconnect layer, the electroconductive pattern applied with a constant potential,

wherein the electroconductive pattern is arranged between the first interconnect and the second interconnect.

2. The semiconductor device according to claim 1 , wherein the electroconductive pattern and the second interconnect overlap in a plan view.

3. The semiconductor device according to claim 1 , wherein the second interconnect is an interconnect which is applied with an electric current having a frequency equal to or greater than 5 GHz.

4. The semiconductor device according to claim 1 , wherein the second interconnect functions as an inductor.

5. The semiconductor device according to claim 1 , wherein the constant potential is a ground potential.

6. A semiconductor device comprising:

an interconnect substrate including a first interconnect; and

a semiconductor chip mounted on the interconnect substrate, the semiconductor chip including:

a substrate;

an interconnect layer provided on a surface of the substrate;

a second interconnect provided in the interconnect layer, the second interconnect formed to have an electric coil-shape; and

an electroconductive shield formed on the interconnect layer, the electroconductive shield applied with a constant potential,

wherein the electroconductive shield is arranged between the first interconnect and the second interconnect.

7. The semiconductor device according to claim 6 , wherein the electroconductive shield and the second interconnect overlap in a plan view.

8. The semiconductor device according to claim 6 , wherein the second interconnect is an interconnect which is applied with an electric current having a frequency equal to or greater than 5 GHz.

9. The semiconductor device according to claim 6 , wherein the second interconnect functions as an inductor.

10. The semiconductor device according to claim 6 , wherein the constant potential is a ground potential.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2012
From: NAKASHIBA, YASUTAKA
To: NEC ELECTRONICS CORPORATION
Reel/Frame 028601/0275 →
CHANGE OF NAME Recorded Jul 20, 2012
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 028601/0417 →
Priority Claims (1)
JP 2007-051728 · Mar 1, 2007 · national
Continuity (4)
Division 13045198 · Mar 10, 2011
Division 12429556 · Apr 24, 2009
Division 12040952 · Mar 3, 2008
Related Publication 20120286403A1 · Nov 15, 2012