Successive approximation register ADC circuits and methods
A non-binary successive approximation analogue to digital converter, for converting using successive conversion steps, is operable in first and second modes. The first and second modes have different noise properties and the converter is switched between the modes during the conversion process.
1. A non-binary successive approximation analogue to digital converter for converting using successive conversion steps, the converter comprising
a sample and hold unit, a comparator, a logic unit, a digital to analogue converter, a preamplifier between the sample and hold unit and the comparator, and one or more capacitors which are switchable in or out of circuit at an output of the preamplifier for changing noise properties, wherein
the logic unit and the digital to analogue converter are in a feedback path around the comparator, and
the converter is operable in first and second modes, the first and second modes having different noise properties and the converter is operable to switch between the first and second modes during the conversion process.
2. A converter as claimed in claim 1 , further comprising an element for adjusting a duration of the conversion steps such that different durations are used in the first and second modes.
3. A converter as claimed in claim 2 , further comprising a clock circuit having an output, wherein the device for adjusting comprises a clock divider for reducing a frequency of the clock circuit output, and a multiplexer is provided for selecting the clock circuit output or the frequency-reduced clock.
4. A converter as claimed in claim 1 , further comprising an element for changing a bias current for changing the noise properties.
5. A converter as claimed in claim 1 , further comprising a tunable electrical supply voltage for changing the noise properties.
6. A converter as claimed in claim 1 , wherein the noise property comprises a total noise power integrated across an operation bandwidth.
7. A time-interleaved analog to digital converter comprising a plurality of successive approximation analog to digital converters according to claim 1 .
8. The time-interleaved analog to digital converter of claim 7 , further comprising 64 successive approximation analog to digital converters, wherein the time-interleaved analog to digital converter is operable at 2.6 Gigasamples per second.
9. A telecommunication receiver comprising a time-interleaved analog to digital converter, according to claim 7 .
10. A method of controlling a non-binary successive approximation analog to digital converter, the converter comprising a sample and hold unit, a comparator, a logic unit, a digital to analogue converter, a preamplifier between the sample and hold unit and the comparator, and one or more capacitors which are switchable in or out of circuit at an output of the preamplifier for changing noise properties, the method comprising:
operating the converter in first and second modes during a conversion process using successive conversion steps by switching the one or more capacitors in or out of circuit, the modes having different noise properties.
11. A method as claimed in claim 10 , wherein a first batch of conversion steps are performed with the first mode of operation, with a first noise level, and a second later batch of conversion steps are performed with the second mode of operation, with a smaller, second noise level.
12. A method as claimed in claim 10 , further comprising adjusting durations of the conversion steps such that different durations are used in the first and second modes.
13. A method as claimed in claim 10 , further comprising reducing a frequency of a clock signal, and selecting the clock signal or the frequency-reduced clock signal for the conversion process, depending on the mode.