A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal, and a delay circuit for delaying the phase of the output signal output from the oscillator to a load circuit, wherein the delay circuit is provided outside the feedback loop.
1. A phase locked loop (PLL) circuit, comprising:
a phase comparator configured to compare a phase of a first reference signal with a phase of a feedback signal;
a charge pump circuit configured to receive an output of the phase comparator;
a filter configured to smooth an output of the charge pump circuit;
a voltage-current converter configured to convert an output of the filter to a current signal;
a current controlled oscillator configured to output an output signal at a frequency in accordance with the current signal;
a feedback loop configured to return the output signal of the oscillator and supply the output signal as the feedback signal; and
a delay circuit configured to delay a second reference signal and supply the delayed second reference signal to the phase comparator as the first reference signal;
wherein the delay circuit is provided outside the feedback loop; and
wherein the delay circuit is controlled based on an output of the voltage-current converter.
2. A phase locked loop (PLL) circuit according to claim 1 further comprising,
a first divider configured to divide a frequency of a third reference signal and supply the divided third reference signal having a divided frequency to the delay circuit as the second reference signal.
3. A phase locked loop (PLL) circuit according to claim 1 further comprising,
a second divider configured to divide a frequency of an output from the current controlled oscillator and supply an output signal having a divided frequency to the phase comparator as the feedback signal.
4. A phase locked loop (PLL) circuit according to claim 1 , wherein an idling current is supplied to the delay circuit in addition to the output of the voltage-current converter.