IP Library Granted Patent US 9,513,912
Granted Patent B2
US 9,513,912 · App. 13/560,279 · Granted Dec 6, 2016

Memory controllers

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Quick Facts
Patent No.
US 9,513,912
App. No.
13/560,279
Granted
Dec 6, 2016
Kind
B2
Abstract

Methods and controllers for executing an instruction set are provided. In one such method, executing an instruction set includes executing an instruction of one type in the instruction set, executing a context switch instruction, and executing an instruction of a second type in the instruction set. in one such controller, a single machine executes instructions in an instruction set with instructions having an operational code, and instructions that do not have an operational code.

Claims (55)

1. A method of executing an instruction set, comprising:

executing, in a controller using a first mode of interpreting portions of an instruction, an instruction of one type in the instruction set, wherein each instruction of the instruction set has a same length;

executing, in the controller, a context switch instruction to change a mode of operation of the controller to use a second, different, mode of interpreting portions of an instruction after executing the instruction of the one type; and

executing, in the controller using the second mode of interpreting portions of an instruction, an instruction of a second, different, type in the instruction set only after executing the context switch instruction;

wherein the context switch instruction is an instruction of the instruction set.

2. The method of claim 1 , wherein executing instructions of the one type in the instruction set comprises executing instructions having an operational code.

3. The method of claim 1 , wherein executing instructions of the second type in the instruction set comprises executing instructions that do not have an operational code.

4. The method of claim 1 , wherein executing an instruction of the one type in the instruction set comprises executing control flow instructions in the controller.

5. The method of claim 1 , wherein executing an instruction of the second type in the instruction set comprises executing control flow instructions in the controller.

6. The method of claim 1 , and further comprising:

executing, in the controller, an exit from context instruction to change the mode of operation of the controller to a prior mode of operation used to execute the instruction of the one type in the instruction set using the first mode of interpreting portions of an instruction;

wherein the exit from context instruction is an instruction of the instruction set.

7. The method of claim 1 , wherein instructions of the instruction set are executed on a 16 bit controller.

8. The method of claim 1 , wherein instructions of the instruction set comprise 16 bit instructions.

9. A method for executing an instruction set, comprising:

running a first portion of the instruction set using a first mode of operation of a controller, wherein running the first portion of the instruction set comprises executing the first portion of the instruction set in the controller using the first mode of operation;

running a second portion of the instruction set using a second mode of operation of the controller, wherein running the second portion of the instruction set comprises executing the second portion of the instruction set in the controller using the second mode of operation;

determining whether a subsequent instruction to be executed in the controller belongs to a different one of the first and second portions of the instruction set than a prior instruction executed in the controller; and

when it is determined that the subsequent instruction belongs to a different one of the first and second portions of the instruction set than the prior instruction, changing the mode of operation of the controller prior to executing the subsequent instruction;

wherein the controller is a single machine controller; and

wherein each instruction of the instruction set has a same length.

10. The method of claim 9 , and further comprising:

switching modes upon receipt of a context instruction as part of the first portion of the instruction set.

11. The method of claim 9 , wherein the first mode is an execution flow control mode.

12. The method of claim 9 , wherein the second mode is a macro sequencer mode.

13. The method of claim 9 , wherein the second mode of the controller is started when a macro call is made in a first portion of the instruction set.

14. The method of claim 13 , wherein the first mode of the controller is restarted at completion of the macro code.

15. The method of claim 10 , and further comprising changing back to the first mode on receipt of an exit from context instruction.

16. A controller, comprising:

a read only memory for storing instructions comprising an instruction set, wherein each instruction of the instruction set has a same length;

a register to load instructions of the instruction set therein; and

a control unit to execute instructions of the instruction set loaded into the register, the control unit configured to switch between execution of instructions of one type using a first execution mode with a first mode of interpreting instructions and execution of instructions of another type using a second execution mode with a different mode of interpreting instructions upon receipt of a context switch instruction of the instruction set that is solely designated to change the execution mode of the control unit.

17. The controller of claim 16 , wherein the control unit executes the first execution mode as an execution flow control mode.

18. The controller of claim 16 , wherein the control unit executes the second execution mode as a macro sequencer mode.

19. The controller of claim 16 , wherein the control unit is further configured to start the second mode of the controller when a macro call is made in the first instruction set.

20. The controller of claim 19 , wherein the control unit is further configured to restart the first mode upon receipt of an exit from context instruction.

21. The compiler of claim 16 , wherein the register is a 16-bit register.

22. A memory device, comprising:

an array of memory cells;

a controller, comprising:

a single machine, wherein the single machine is configured to execute instructions in a first instruction set and instructions in a second instruction set, wherein the single machine is further configured to use a first mode of interpreting instructions in the first instruction set and to use a different mode of interpreting instructions of the second instruction set, wherein the first instruction set comprises instructions having an operational code, and the second instruction set comprises instructions that do not have an operational code, and wherein instructions of the first instruction set each have a particular length and instructions of the second instruction set each have the particular length.

23. A controller, comprising:

a control unit; and

an instruction set, the instruction set comprising an instruction only configured to cause the control unit to switch a context of executing instructions of the instruction set of a first type using a first mode of interpreting instructions to executing instructions of the instruction set of a second type different than the first type using a different mode of interpreting instructions.

24. The controller of claim 23 , wherein the control unit has a configuration to perform a method, the method comprising:

executing an instruction of the instruction set of the first type using the first mode of interpreting instructions;

executing the context switch instruction; and

executing an instruction of a second type in the instruction set the instruction set of the second type using the different mode of interpreting instructions.

25. A controller comprising:

a single machine controller, wherein the single machine controller is configured to interpret and execute instructions of a first instruction type and interpret and execute instructions of a second instruction type different than the first instruction type, wherein the single machine controller is further configured to interpret an instruction of the first instruction type having a particular value to be a different instruction than an instruction of the second instruction type having the particular value, wherein the first instruction type comprises instructions having an operational code, wherein the second instruction type comprises instructions that do not have an operational code, and wherein instructions of the first instruction type and instructions of the second instruction type have a same length.

26. The method of claim 1 , wherein using the first mode of interpreting portions of an instruction comprises determining that a first instruction having a particular value is an instruction to perform a particular action, and wherein using the second mode of interpreting portions of an instruction comprises determining that a second instruction having the particular value is an instruction to perform a different action.

27. The method of claim 1 , further comprising:

executing, in the controller, a second context switch instruction to change the mode of operation of the controller to use an additional mode of interpreting portions of an instruction that is different from the first and second modes of interpreting portions of an instruction; and

executing, in the controller using the additional mode of interpreting portions of an instruction, an instruction of a third type in the instruction set, different from the first and second types in the instruction set, only after executing the second context switch instruction;

wherein the second context switch instruction is an instruction of the instruction set.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2012
From: DE SANTIS, LUCA; GALLESE, MARIA-LUISA; SIRIZOTTI, EMANUELE; DI-FRANCESCO, WALTER
To: MICRON TECHNOLOGY, INC.
Reel/Frame 028830/0594 →