Advanced/enhanced protocol circuitry connected to TCK, TMS, and topology circuitry
Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.
1. An integrated circuit comprising:
A. a test data in lead and a test data out lead;
B. an adapter test access port that is coupled to the test data in lead and the test data out lead, the adapter test access port including an instruction register coupled to the test data in lead and the test data out lead and topology selection logic that is coupled to the test data in lead, the topology selection logic including a topology register containing bit positions indicating that the adapter test access port is connected in one of a series, star 2, star 4 without test data out drive, and star 4 with test data out drive topologies; and
C. a chip level test access port that is coupled to the test data in lead and the test data out lead through the adapter test access port.
2. The integrated circuit of claim 1 in which the topology register has two bit positions.
3. The integrated circuit of claim 1 including an embedded test access port coupled to the test data in lead and the test data out lead though the adapter test access port.