IP Library Granted Patent US 9,146,170
Granted Patent B2
US 9,146,170 · App. 13/562,853 · Granted Sep 29, 2015

Capacitive pressure sensor in an overmolded package

Inventors: Jian Wen (Chandler, AZ); William G. McDonald (Payson, AZ)
Assignee: FREESCALE SEMICONDUCTOR, INC.
G01L19/14
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Quick Facts
Patent No.
US 9,146,170
App. No.
13/562,853
Granted
Sep 29, 2015
Kind
B2
Abstract

An overmolded pressure sensor package is provided. The pressure sensor die (Pcell) is capped so that the Pcell has enhanced rigidity to withstand stress effects produced by the molding encapsulant. The Pcell cap includes a hole located away from the Pcell diaphragm, so that external gas pressure can be experienced by the Pcell, while at the same time directing moisture away from the diaphragm. Gel does not need to be used, and instead a soft film can be deposited on the Pcell to protect the Pcell diaphragm from excess moisture, if needed. The Pcell cap can take the form of, for example, a dummy silicon wafer or a functional ASIC.

Claims (77)

1. A semiconductor device package comprising:

a pressure sensor die comprising a pressure deformable diaphragm disposed at a region of a first major surface of the pressure sensor die;

a shaped cap wafer attached to the first major surface of the pressure sensor die, wherein

a cavity is formed between a portion of the shaped cap wafer and a portion of the first major surface of the pressure sensor die,

the portion of the first major surface of the pressure sensor die comprises the region where the pressure deformable diaphragm is disposed, and

the shaped cap wafer includes a pressure inlet port configured to admit gasses external to the cavity into the cavity;

a package substrate;

an active semiconductor device adhesively coupled to the package substrate at a first major surface of the active semiconductor device, wherein

the pressure sensor die is adhesively coupled to a second major surface of the active semiconductor device, and

the second major surface of the active semiconductor device opposes the first major surface of the active semiconductor device;

an encapsulant over and around the package substrate, over and around the active semiconductor device, over and around the pressure sensor die, and around the shaped cap wafer.

2. The semiconductor device package of claim 1 wherein the pressure inlet port is located in a region of the shaped cap wafer opposing the portion of the first major surface of the pressure sensor die that is not the region including the pressure deformable diaphragm.

3. The semiconductor device package of claim 1 wherein the shaped cap wafer comprises a silicon wafer shaped to form the cavity.

4. The semiconductor device package of claim 1 wherein the shaped cap wafer comprises an active semiconductor device having an external shape configured to form the cavity.

5. The semiconductor device package of claim 1 further comprising:

encapsulant over the shaped cap wafer, wherein the encapsulant is formed to provide a package inlet port over the pressure inlet port of the shaped cap wafer.

6. The semiconductor device package of claim 1 , wherein

the active semiconductor device comprises a control die,

the pressure sensor die is electrically coupled to the control die, and

the control die is configured to receive and process signals generated by the pressure sensor die.

7. A semiconductor device package comprising:

a pressure sensor die comprising a pressure deformable diaphragm disposed at a region of a first major surface of the pressure sensor die;

a shaped cap wafer attached to the first major surface of the pressure sensor die, wherein

a cavity is formed between a portion of the shaped cap wafer and a portion of the first major surface of the pressure sensor die,

the portion of the first major surface of the pressure sensor die comprises the region where the pressure deformable diaphragm is disposed, and

the shaped cap wafer includes a pressure inlet port configured to admit gasses external to the cavity into the cavity;

a package substrate, wherein

the pressure sensor die is adhesively coupled to the package substrate at a second major surface of the pressure sensor die that opposes the first major surface of the pressure sensor die; and

an encapsulant over and around the package substrate, over and around the pressure sensor die, and around the shaped cap wafer.

8. The semiconductor device package of claim 7 further comprising:

an active semiconductor device electrically coupled to the pressure sensor die, wherein

the active semiconductor device is configured to receive and process signals generated by the pressure sensor die, and

at least a portion of the active semiconductor device is encapsulated by the encapsulant.

9. The semiconductor device package of claim 8 wherein the active semiconductor device comprises the shaped cap wafer.

10. The semiconductor device package of claim 9 further comprising:

encapsulant over the shaped cap wafer, wherein the encapsulant is formed to provide a package inlet port over the pressure inlet port of the shaped cap wafer.

11. A semiconductor device package comprising:

a pressure sensor die comprising a pressure deformable diaphragm disposed at a region of a first major surface of the pressure sensor die;

a shaped cap wafer attached to the first major surface of the pressure sensor die, wherein

a cavity is formed between a portion of the shaped cap wafer and a portion of the first major surface of the pressure sensor die,

the portion of the first major surface of the pressure sensor die comprises the region where the pressure deformable diaphragm is disposed, and

the shaped cap wafer includes a pressure inlet port configured to admit gasses external to the cavity into the cavity;

a package substrate, wherein

the package substrate comprises a substrate pressure inlet, and

the shaped cap wafer is adhesively attached to the package substrate such that the substrate pressure inlet and the shaped cap wafer pressure inlet are aligned; and

an encapsulant over and around the package substrate, over and around the shaped cap wafer, and around at least a portion of the pressure sensor die.

12. The semiconductor device package of claim 11 further comprising:

an active semiconductor device electrically coupled to the pressure sensor die, wherein

the active semiconductor device is configured to receive and process signals generated by the pressure sensor die, and

at least a portion of the active semiconductor device is encapsulated by the encapsulant.

13. The semiconductor device package of claim 12 wherein the active semiconductor device is adhesively attached to a second major surface of the pressure sensor die that opposes the first major surface of the pressure sensor die.

14. The semiconductor device package of claim 12 wherein the active semiconductor device comprises the shaped cap wafer.

15. A method for forming a packaged semiconductor device assembly, the method comprising:

providing a surface embodied within the packaged semiconductor device assembly;

affixing a pressure sensor die to a portion of the surface, wherein

the pressure sensor die is affixed to the surface at a first major surface of the pressure sensor die, and

a second major surface of the pressure sensor die, opposing the first major surface, comprises a pressure deformable diaphragm;

affixing a shaped cap wafer to the second major surface of the pressure sensor die, wherein

a cavity is formed between a portion of the shaped cap wafer and a portion of the second major surface of the pressure sensor die and the portion of the second major surface comprises the pressure deformable diaphragm, and

the shaped cap wafer includes a pressure inlet port configured to admit gasses external to the cavity into the cavity; and

forming an encapsulated region over and around the pressure sensor die and the shaped cap wafer, wherein

said forming is performed to provide a package inlet port over the pressure inlet port of the shaped cap wafer, and

the package inlet port is configured to admit gasses external to the encapsulant into the cavity through the pressure inlet port of the shaped cap wafer.

16. The method of claim 15 further comprising:

performing said forming the encapsulated region using a film-assisted molding technique to form the package inlet port.

17. A tire pressure monitoring system comprising:

a wheel module, configured to be mounted in a vehicle tire, comprising

a process controller configured to process signals from one or more sensors,

a pressure sensor die, coupled to the process controller, and comprising a pressure deformable diaphragm disposed at a region of a first major surface of the pressure sensor die,

a shaped cap wafer adhesively coupled to the first major surface of the pressure sensor die, wherein

a cavity is formed between a portion of the shaped cap wafer and a portion of the first major surface of the pressure sensor die,

the portion of the first major surface of the pressure sensor die comprises the region where the pressure deformable diaphragm is disposed, and

the shaped cap wafer includes a pressure inlet port configured to admit gasses external to the cavity into the cavity, and

a package substrate, wherein the pressure sensor die is adhesively coupled to the package substrate at a second major surface of the pressure sensor die that opposes the first major surface of the pressure sensor die, and

an encapsulant over and around the package substrate, over and around the pressure sensor die, and around the shaped cap wafer, and

a radio-frequency (RF) transmitter, coupled to the process controller, configured to transmit sensor information provided by the process controller.

18. The tire pressure monitoring system of claim 17 wherein the shaped cap wafer comprises a silicon wafer shaped to form the cavity.

Assignments (23)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2026
From: NXP USA, INC.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 075045/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0614 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0633 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0652 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030256/0471 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030256/0544 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030256/0625 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2012
From: WEN, JIAN; MCDONALD, WILLIAMS G.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 028708/0192 →
Continuity (1)
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