IP Library Granted Patent US 8,816,459
Granted Patent B2
US 8,816,459 · App. 13/563,620 · Granted Aug 26, 2014

Image sensor having wave guide and method for manufacturing the same

Inventors: In-Gyun Jeon (Seongnam-si, KR); Se-Jung Oh (Seoul, KR); Heui-Gyun Ahn (Seongnam-si, KR); Jun-Ho Won (Seoul, KR)
Assignee: Siliconfile Technologies Inc.
H01L27/14627H01L27/14687H01L27/14632H01L27/14643H01L27/14621H01L27/14685
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Quick Facts
Patent No.
US 8,816,459
App. No.
13/563,620
Granted
Aug 26, 2014
Kind
B2
Abstract

An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.

Claims (21)

1. A method for manufacturing an image sensor having a wave guide, comprising the steps of:

(a) forming an anti-reflective layer on a semiconductor substrate which is formed with a photodiode and a peripheral circuit region;

(b) forming an insulation layer on the anti-reflective layer;

(c) forming a conductive wiring layer on the insulation layer;

(d) forming at least one interlayer dielectric on the wiring layer;

(e) selectively etching the interlayer dielectric until the wiring layer, is exposed, so as to form a wave guide over the photodiode; and

(f) selectively etching the wiring layer exposed in the step (e) until a portion of the insulation layer formed over the photodiode is exposed;

wherein the wiring layer provides a conductor that allows plasma-charged ions in the wave guide to be discharged into the semiconductor substrate and not be introduced into the photodiode.

2. The method according to claim 1 , wherein the step (c) comprises the step of:

(c1) connecting the wiring layer to a well which is formed in the semiconductor substrate.

3. The method according to claim 2 , wherein the step (d) comprises the step of:

(d1) forming a passivation layer on an uppermost interlayer dielectric.

4. The method according to claim 2 , wherein the well is formed through N+/P junction when the semiconductor substrate is a P type substrate, and is formed through P+/N junction when the semiconductor substrate is an N type substrate.

5. The method according to claim 2 , wherein, in the step (c), the wiring layer is formed using tungsten (W), aluminum (Al), or titanium (Ti).

6. The method according to claim 2 , further comprising the step of:

(g) etching a portion of the insulation layer exposed in the wiring layer etching step.

7. The method according to claim 2 , further comprising the steps of:

(h) forming a color filter on the passivation layer; and

(i) forming a microlens on the color filter.

8. The method according to claim 1 , wherein the wiring layer acts as a etch stop layer in the course of forming a wave guide so that non-uniformity in etching depth can be avoided.

9. The method according to claim 2 , wherein the wiring layer allows plasma-charged ions in the wave guide to be discharged into the semiconductor substrate via the well formed in the semiconductor substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 20, 2017
From: SILICONFILE TECHNOLOGIES INC.
To: SK HYNIX INC.
Reel/Frame 041023/0058 →
Priority Claims (1)
KR 10-2009-0033400 · Apr 17, 2009 · national
Continuity (2)
Division 12758646 · Apr 12, 2010
Related Publication 20120295389A1 · Nov 22, 2012