Partial block memory operations
View Patent ↗Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.
1. An apparatus comprising a block of memory cells, the block of memory cells comprising:
strings of charge storage devices, each string comprising charge storage devices formed in a. plurality of tiers;
multiple memory tile columns, wherein each of the multiple memory tile columns includes a number of the strings of charge storage devices wherein each of the strings is only within a single one of the multiple memory tile columns;
global access lines shared by the strings, each global access line configured to be coupled to the charge storage devices within a selected one of the multiple memory tile columns through a sub-access line coupled to a respective tier of the plurality of tiers within the selected one of the multiple memory tile column, wherein the sub-access line is one of access lines coupled to the multiple memory tile columns;
a separate sub-source coupled to each of the multiple memory tile columns, each sub-source coupled to a source select gate (SGS) of each string within respective ones of the multiple memory tile columns, each sub-source independently selectable from other sub-sources to select the strings of its respective memory tile column independently of other strings corresponding to other memory tile columns;
sub-source select gate (sub-SGS) lines, each sub-SGS line coupled to the SGS of each string of respective memory tile column , each sub-SGS line independently selectable from other sub-SGS lines corresponding to other strings in other memory tile columns; and
sub-drain select gate (sub-SGD) lines, each sub-SGD line coupled to a drain select gate (SGD) of each string of a respective memory tile column , wherein each sub-SGD line is independently selectable from other sub-SGD lines corresponding to other strings in other memory tile columns, wherein:
the multiple memory tile columns include a first memory tile column coupled to a first sub-source, and a second multiple memory tile column coupled to a second sub-source;
the sub-access lines include first sub-access lines and second access lines;
charge storage devices in each tier of the plurality of tiers in the first memory tile column is coupled to one of the first sub-access lines;
charge storage devices in each tier of the plurality of tiers in the second memory tile column is coupled to one of the second sub-access lines; and
the first sub-access lines are electrically separated from the second access lines.
2. The apparatus of claim 1 , wherein each of the memory tile columns is selectable independently of the other memory tile columns to concurrently perform a memory operation on the charge storage devices corresponding to the selected memory tile column while refraining from performing the memory operation on the charge storage devices corresponding to non-selected ones of the memory tile columns.
3. The apparatus of claim 1 , wherein the charge storage devices coupled by a respective sub-access line of the sub-access lines comprise a respective memory tile of the multiple memory tile columns.
4. The apparatus of claim wherein ac the access lines is coupled to its sub-access lines via sub-string drivers.
5. The apparatus of claim 1 , further comprising:
sub-source drivers, each sub-source driver coupled to a respective sub-source of the sub sources, and each sub-source driver to apply a control signal to the respective sub-source independently of other sub-source drivers corresponding to other sub-sources.
6. The apparatus of claim 1 , wherein each sub-source is coupled to a respective power source.
7. The apparatus of claim 1 , wherein the multiple memory tile columns comprise sector columns.
8. The apparatus of claim 1 , further comprising sub-SGS drivers, each sub-SGS driver coupled to a respective sub-SGS line to apply a control signal to the respective sub-SGS line independently of other sub-SGS drivers corresponding to other sub-SGS lines.
9. The apparatus of claim 1 , further comprising sub-SGD drivers, each sub-SGD driver coupled to a respective sub-SGD line to apply a control signal to the respective sub-SGD line independently of other sub-SGD drivers corresponding to other sub-SGD lines.
10. The apparatus of claim 1 , further comprising data lines, each data line coupled to a drain select gate (SGD) of a respective string of the strings, the data lines comprising subsets of data lines, each of the subsets of the data lines corresponding to a respective sub-source of the sub-sources.
11. The apparatus of claim 10 , wherein each data line of the plurality of data lines is coupled to a respective plurality of strings of charge storage devices including the respective string.
12. An apparatus comprising:
a first memory block and a second memory block, each of the first memory block and the second memory block including:
strings of charge storage devices, each string comprising charge storage devices formed in a plurality of tiers;
global access lines shared by the strings, each global access line configured to be coupled to the charge storage devices within a selected one of the first memory block and the second memory block through a sub-access line coupled to a respective tier of the plurality of tiers within the selected one of the first memory block and the second memory block, wherein the sub-access line is one of access lines coupled to the plurality of tiers within the selected one of the first memory block and the second memory block; and
sub-drain select gate (sub-SGD) lines, each sub-SGD line coupled to a drain select gate (SGD) of each string of a respective one of the first memory block and the second memory block, wherein each sub-SGD line is independently selectable from other sub-SGD lines corresponding to other strings in the other memory block, wherein:
the sub-access lines include first sub-access lines and second access lines;
charge storage devices in each tier of the plurality of tiers in a first block portion of a selected one of the first memory block and the second memory block is coupled to one of the first sub-access lines;
charge storage devices in each tier of the plurality of tiers in a second block portion of the selected one of the first memory block and the second memory block is coupled to one of the second sub-access lines; and
the first sub-access lines are electrically separated from the second access lines.
13. The apparatus of claim 12 , further comprising sub-SGD drivers, each sub-SGD driver coupled to a respective sub-SGD line of the sub-SGD lines to apply a control signal to the respective sub-SGD line independently of other sub-SGD drivers corresponding to other SGD lines.
14. The apparatus of claim 12 , further comprising a separate sub-source coupled to each of the first memory block and the second memory block, each sub-source coupled to a source select gate (SGS) of each string within respective ones of the first memory block and the second memory block, each sub-source independently selectable from other sub-sources to select the strings of its respective memory tile column independently of the other memory block.