System and method for detecting integrated circuit anomalies

1. A system for testing integrated circuits for presence of anomalies, the system comprising:

at least one circuit configured to:

apply a plurality of inputs to a manufactured integrated circuit under test to obtain a plurality of measurements consisting of N measurements at least partially characterizing power leakage in the manufactured integrated circuit under test,

encode the plurality of measurements using a compressive sensing encoding technique at least in part by generating a plurality of random linear combinations of measurements in the plurality of measurements to obtain a plurality of encoded measurements consisting of M encoded measurements, wherein M and N are integers and M is smaller than N, and

provide the plurality of encoded measurements to an external device external to the at least one circuit; and

at least one processor housed in the external device and configured to:

receive the plurality of encoded measurements; and

determine whether the manufactured integrated circuit under test contains at least one anomaly based, at least in part, on the plurality of encoded measurements.

2. The system of claim 1 , wherein generating the plurality of random linear combinations comprises:

computing at least one weighted sum of measurements in the plurality of measurements, with measurements being weighted by random weights obtained at least in part by using at least one probability distribution.

3. The system of claim 1 , wherein M is less than half of N.

4. The system of claim 1 , wherein the at least one processor is configured to:

decode the plurality of encoded measurements, at least in part by using a compressive sensing decoding technique, to obtain a plurality of decoded measurements.

5. The system of claim 4 , wherein the at least one processor is configured to determine whether the manufactured integrated circuit under test contains the at least one anomaly, at least in part, by:

determining whether at least one decoded measurement in the plurality of decoded measurements indicates a level of power leakage in the manufactured integrated circuit under test that substantially deviates from characteristic levels of power leakage in an anomaly-free integrated circuit corresponding to the manufactured integrated circuit under test.

6. The system of claim 1 , wherein when the at least one processor determines that the manufactured integrated circuit under test contains the at least one anomaly, the at least one processor is further configured to:

identify a location of the at least one anomaly in the manufactured integrated circuit under test.

7. The system of claim 1 , wherein the at least one circuit comprises the manufactured integrated circuit under test.

8. At least one circuit used for testing integrated circuits for presence of anomalies, the at least one circuit configured to:

apply a plurality of inputs to a manufactured integrated circuit under test to obtain a plurality of measurements consisting of N measurements at least partially characterizing power leakage in the manufactured integrated circuit under test;

encode the plurality of measurements using a compressive sensing encoding technique at least in part by generating a plurality of random linear combinations of measurements in the plurality of measurements to obtain a plurality of encoded measurements consisting of M encoded measurements, wherein M and N are integers and M is smaller than N; and

provide the plurality of encoded measurements to an external device external to the at least one circuit.

9. The at least one circuit of claim 8 , wherein generating the plurality of random linear combinations comprises:

computing at least one weighted sum of measurements in the plurality of measurements, with measurements being weighted by random weights obtained at least in part by using at least one probability distribution.

10. The at least one circuit of claim 9 , further comprising circuitry configured to generate the plurality of inputs and the weights.

11. The at least one circuit of claim 8 , wherein M is less than half of N.

12. The at least one circuit of claim 11 , wherein M is less than 25 percent of N.

13. The at least one circuit of claim 12 , wherein M is less than 10 percent of N.

14. A method for testing integrated circuits for presence of anomalies, the method comprising:

applying, by at least one circuit, a plurality of inputs to a manufactured integrated circuit under test to obtain a plurality of measurements consisting of N measurements at least partially characterizing power leakage in the manufactured integrated circuit under test;

encoding, by the at least one circuit, the plurality of measurements using a compressive sensing encoding technique at least in part by generating a plurality of random linear combinations of measurements in the plurality of measurements to obtain a plurality of encoded measurements consisting of M encoded measurements, wherein M and N are integers and M is smaller than N;

providing, by the at least one circuit, the plurality of encoded measurements to an external device external to the at least one circuit;

receiving, by the external device, the plurality of encoded measurements; and

determining, by the external device, whether the manufactured integrated circuit under test contains at least one anomaly based, at least in part, on the plurality of encoded measurements.

15. The method of claim 14 , wherein generating the plurality of random linear combinations comprises:

computing at least one weighted sum of measurements in the plurality of measurements, with measurements being weighted by random weights obtained at least in part by using at least one probability distribution.

16. The method of claim 15 , wherein the at least one probability distribution is a distribution of a Bernoulli random variable or of a Gaussian random variable.

17. The method of claim 14 , wherein M is less than half of N.

18. The method of claim 14 , further comprising:

decoding the plurality of encoded measurements, at least in part by using a compressive sensing decoding technique, to obtain a plurality of decoded measurements.

19. The method of claim 18 , wherein the determining comprises determining whether at least one decoded measurement in the plurality of decoded measurements indicates a level of power leakage in the manufactured integrated circuit under test that substantially deviates from characteristic levels of power leakage in a corresponding anomaly-free integrated circuit.

20. The method of claim 14 , further comprising:

identifying a location of the at least one anomaly in the manufactured integrated circuit under test, when it is determined that the manufactured integrated circuit under test contains the at least one anomaly.