Vector processing in an active memory device

1. A method for vector processing in an active memory device that includes memory and a processing element, the method comprising:

decoding, in the processing element, an instruction comprising a plurality of sub-instructions to execute in parallel;

determining an iteration count to repeat execution of the sub-instructions in parallel based on decoding an iteration count source field of the instruction that defines whether to set the iteration count based on an iteration count field of the instruction or based on an iteration count register;

repeating execution of the sub-instructions in parallel for multiple iterations, by the processing element, based on the iteration count;

accessing multiple locations in the memory in parallel based on the execution of the sub-instructions;

identifying a lane control sub-instruction in the instruction based on the decoding of the instruction, the lane control sub-instruction controlling a sequence of instruction execution and positioned in parallel with the sub-instructions to execute in parallel; and

executing the lane control sub-instruction, by the processing element, only once after execution of the sub-instructions is performed in parallel for multiple iterations.

2. The method of claim 1 , wherein the sub-instructions comprise at least a pair of a memory access sub-instruction in parallel with an arithmetic-logical sub-instruction, and further comprising:

flowing the memory access sub-instruction to a load-store unit in the processing element; and

flowing the arithmetic-logical sub-instruction to an arithmetic logic unit in the processing element to execute the memory access sub-instruction in parallel with the arithmetic-logical sub-instruction.

3. The method of claim 2 , further comprising:

accessing one or more of: a vector computation register file and a scalar computation register file in the processing element for operands to execute the memory access sub-instruction in the load-store unit; and

accessing one or more of: the vector computation register file and the scalar computation register file in the processing element for operands to execute the arithmetic-logical sub-instruction in the arithmetic logic unit.

4. The method of claim 3 , further comprising:

partitioning at least one of the operands as a plurality of sub-elements based on a data type of the arithmetic-logical sub-instruction;

performing, by the arithmetic logic unit, an operation of the arithmetic-logical sub-instruction in parallel execution slots on each of the sub-elements; and

computing, by the load-store unit, an address per sub-element.

5. The method of claim 3 , further comprising:

flowing an output of the load-store unit to one or more of: the load-store unit, an effective-to-real address translation unit, a load-store queue, the vector computation register file, and the scalar computation register file; and

flowing an output of the arithmetic logic unit to one or more of: the arithmetic logic unit, the load-store unit, the vector computation register file, and the scalar computation register file.

6. The method of claim 3 , wherein the processing element is partitioned into multiple processing slices operable in parallel, each processing slice comprising a pair of the load-store unit and the arithmetic logic unit, and an associated pair of the vector computation register file and the scalar computation register file, the method further comprising:

flowing an output of the arithmetic logic unit of one processing slice to an input of one or more of: the load-store unit and the arithmetic logic unit.

7. The method of claim 3 , further comprising:

performing an error check on the operands prior to executing the memory access sub-instruction and the arithmetic-logical sub-instruction.

8. The method of claim 1 , wherein

the lane control sub-instruction is a branch sub-instruction executed by the processing element during execution of a last iteration of the instruction based on conditions evaluated during execution of a first element of the instruction.

9. A method for vector processing in an active memory device that includes memory and a processing element, the method comprising:

receiving, in the processing element, a command from a requestor;

fetching, in the processing element, an instruction based on the command, the instruction being fetched from an instruction buffer in the processing element;

decoding, in the processing element, the instruction comprising a plurality of sub-instructions to execute in parallel;

determining an iteration count to repeat execution of the sub-instructions in parallel based on decoding an iteration count source field of the instruction that defines whether to set the iteration count based on an iteration count field of the instruction or based on an iteration count register;

repeating execution of the sub-instructions in parallel for multiple iterations, by the processing element, based on the iteration count;

accessing multiple locations in the memory in parallel based on the execution of the sub-instructions;

identifying a lane control sub-instruction in the instruction based on the decoding of the instruction, the lane control sub-instruction controlling a sequence of instruction execution and positioned in parallel with the sub-instructions to execute in parallel; and

executing the lane control sub-instruction, by the processing element, only once after execution of the sub-instructions is performed in parallel for multiple iterations.

10. The method of claim 9 , wherein the requestor comprises one of: a main processor, a network interface, an I/O device, and an additional active memory device, configured to communicate with the active memory device.

11. The method of claim 9 , further comprising:

fetching a special instruction from the instruction buffer to load a new instruction from the memory; and

replacing an entry in the instruction buffer with the new instruction based on executing the special instruction.

12. The method of claim 9 , wherein the active memory device is a three-dimensional memory cube, the memory is divided into three-dimensional blocked regions as memory vaults, and accessing multiple locations in the memory is performed through one or more memory controllers in the active memory device.

13. The method of claim 9 , wherein the sub-instructions comprise at least a pair of a memory access sub-instruction in parallel with an arithmetic-logical sub-instruction, and the method further comprises:

flowing the memory access sub-instruction to a load-store unit in the processing element; and

flowing the arithmetic-logical sub-instruction to an arithmetic logic unit in the processing element to execute the memory access sub-instruction in parallel with the arithmetic-logical sub-instruction.

14. The method of claim 13 , further comprising:

accessing one or more of: a vector computation register file and a scalar computation register file in the processing element for operands to execute the memory access sub-instruction in the load-store unit; and

accessing one or more of: the vector computation register file and the scalar computation register file in the processing element for operands to execute the arithmetic-logical sub-instruction in the arithmetic logic unit.

15. The method of claim 14 , further comprising:

partitioning at least one of the operands as a plurality of sub-elements based on a data type of the arithmetic-logical sub-instruction;

performing, by the arithmetic logic unit, an operation of the arithmetic-logical sub-instruction in parallel execution slots on each of the sub-elements; and

computing, by the load-store unit, an address per sub-element.

16. The method of claim 14 , further comprising:

performing an error check on the operands prior to executing the memory access sub-instruction and the arithmetic-logical sub-instruction;

based on detecting a correctable error, freezing instruction processing, fixing the correctable error, and resuming instruction processing; and

based on detecting an uncorrectable error, freezing instruction processing and notifying a main processor.

17. The method of claim 14 , further comprising:

generating an address for the memory access sub-instruction;

translating the generated address to a real address of the memory;

checking for an address translation fault based on translating the generated address; and

based on identifying the address translation fault, freezing instruction processing, notifying the main processor, waiting for a response from the main processor, fixing a problem causing the address translation fault, and resuming instruction processing.

18. The method of claim 14 , further comprising:

detecting an exception based on executing the arithmetic-logical sub-instruction; and

based on detecting the exception, freezing instruction processing and notifying the main processor.

19. The method of claim 14 , further comprising:

decrementing the iteration count based on executing the memory access sub-instruction and the arithmetic-logical sub-instruction;

based on decrementing the iteration count to zero, decoding lane control sub-instruction from the instruction;

based on determining that the lane control sub-instruction is one of: a return sub-instruction and a pause sub-instruction, freezing instruction processing and notifying a main processor; and

based on determining that the lane control sub-instruction is one of: a branch sub-instruction and a no-operation sub-instruction, adjusting a current instruction address to identify a next instruction in the instruction buffer.