Granted Patent B2

US 8,552,515 · App. 13/569,735 · Granted Oct 8, 2013

Abstract

Claims (163)

1. A method for forming an integrated circuit device on a substrate comprising:

forming a first insulating layer on said substrate;

removing a portion of said first insulating layer to produce an opening to an exposed surface of said substrate therein;

forming first spacers on sidewalls of said opening;

forming a first conductive layer on said exposed surface of said substrate separated from said first spacers on said sidewalls of said opening by a gap therebetween;

forming a bottom electrode of a ferroelectric capacitor over said first conductive layer and in said gap laterally of said first conductive layer;

forming a second insulating layer adjoining said spacers in said opening;

forming second spacers on said second insulating layer in said opening;

forming a ferroelectric dielectric on said bottom electrode between said second spacers;

forming a top electrode on said ferroelectric dielectric;

forming a bottom electrode contact opening through a portion of said second insulating layer to said bottom electrode;

and forming a first electrical contact to said top electrode and a second electrical contact to said bottom electrode through said bottom electrode contact opening.

2. The method of claim 1 further comprising:

providing at least one contact stud in said substrate extending to said exposed surface of said substrate in said opening.

3. The method of claim 1 wherein said step of forming first spacers on said sidewalls of said opening comprises:

depositing a first spacer material over said first insulating layer; and

removing said first spacer material except on said sidewalls of said opening.

4. The method of claim 3 wherein said first spacer material comprises Al 2 O 3 .

5. The method of claim 3 wherein said step of depositing is carried out by chemical vapor deposition.

6. The method of claim 1 wherein said step of forming said first conductive layer comprises:

depositing a first conductive layer material over said first insulating layer and said first spacers; and

removing said first conductive layer material except on said exposed surface of said substrate separated from said first spacers by said gap.

7. The method of claim 6 wherein said first conductive layer material comprises Ti 1-X Al X N.

8. The method of claim 6 wherein said step of depositing is carried out by chemical vapor deposition.

9. The method of claim 1 wherein said step of forming said bottom electrode comprises:

depositing a bottom electrode material over said first insulating layer, said first spacers and in said gap laterally of said first conductive layer in said opening; and

removing said bottom electrode material except over said bottom electrode and within said gap.

10. The method of claim 9 wherein said bottom electrode material comprises Pt.

11. The method of claim 9 wherein said step of depositing comprises chemical vapor deposition.

12. The method of claim 1 wherein said step of forming said second insulating layer comprises:

depositing an oxide over said first insulating layer, said first spacers and said bottom electrode;

and removing said oxide except adjoining said first spacers.

13. The method of claim 1 wherein said step of forming said second spacers comprises:

depositing a second spacer material over said first and second insulating layers and said bottom electrode; and

removing said second spacer material except adjoining said second insulting layer in said opening.

14. The method of claim 13 wherein said second spacer material comprises Al 2 O 3 .

15. The method of claim 13 wherein said step of depositing comprises chemical vapor deposition.

16. The method of claim 1 wherein said step of forming said ferroelectric dielectric comprises:

depositing said ferroelectric dielectric material over said bottom electrode; and

annealing said ferroelectric dielectric material.

17. The method of claim 16 wherein said step of depositing is carried out by deposition of one of PZT, PLZT, BST, SBT, STO or other ferroelectric dielectric materials.

18. The method of claim 1 wherein said step of forming said top electrode comprises:

depositing a top electrode material over said ferroelectric dielectric.

19. The method of claim 18 wherein said top electrode material comprises one of Ir, IrOx, Pt, Pd, PdOx, Ru, RuOx, Rh, RhOx, or other compatible noble metals.

20. The method of claim 1 further comprising:

forming a contact layer material over said top electrode.

21. The method of claim 20 wherein said step of forming said contact layer material is carried out by the deposition of Ti/TiN.

22. The method of claim 1 wherein said step of forming a bottom electrode contact opening comprises:

anisotropically etching said portion of said second insulating layer to said bottom electrode.

23. The method of claim 1 wherein said step of forming said first and second electrical contacts comprises:

depositing a conductive layer material over said top electrode and said bottom electrode in said bottom electrode contact opening.

24. The method of claim 23 wherein said step of depositing comprises the steps of:

firstly depositing a first contact material over said top electrode and said bottom electrode adjoining sidewalls of said bottom electrode contact opening; and

secondly depositing said conductive layer material over said first contact material.

25. The method of claim 24 wherein said first contact material comprises Ti/TiN and said conductive layer material comprises W.

26. The method of claim 24 wherein said conductive layer material is deposited by chemical vapor deposition.

27. A method for forming a ferroelectric device on a planar surface of a semiconductor substrate comprising:

forming a relatively thick oxide layer on said planar surface;

selectively etching an opening through said oxide layer in a pattern established by a non-erodible mask;

applying and selectively etching a first aluminum oxide conformal layer to form first spacers on sidewalls of said opening;

depositing a titanium aluminum nitride layer in a lower portion of said opening and separated from said first spacers;

forming a bottom electrode of a ferroelectric capacitor over said first aluminum oxide conformal layer and in contact with said spacers laterally of said first aluminum oxide conformal layer;

depositing, planarizing and selectively removing an oxide material to form an additional oxide layer adjoining said first spacers in said opening;

depositing and selectively etching a second aluminum oxide layer to form second spacers on said additional oxide layer;

depositing and etching a ferroelectric layer on said bottom electrode between said second spacers;

forming a top electrode on said ferroelectric layer;

forming a Ti/TiN and W contact to said bottom electrode through said oxide material; and

also substantially concurrently forming a Ti/TiN and W contact to said top electrode.

28. The method of claim 27 wherein said non-erodible mask comprises photoresist.

29. The method of claim 27 wherein said step of applying and selectively etching said first aluminum oxide conformal layer comprises:

chemical vapor deposition of aluminum oxide over said relatively thick oxide layer and within said opening;

and removal of said aluminum oxide from said relatively thick oxide layer and the planar surface of said substrate leaving said first spacers.

30. The method of claim 29 wherein said step of removal of said aluminum oxide comprises a directional reactive ion etch process.

31. The method of claim 27 wherein said step of depositing a titanium aluminum nitride layer comprises:

chemical vapor deposition of titanium aluminum nitride over said relatively thick oxide layer and within said opening; and

removal of said titanium aluminum nitride from said relatively thick oxide layer and said first spacers.

32. The method of claim 31 wherein said step of removal of said titanium aluminum nitride comprises a wet etch process.

33. The method of claim 27 wherein said step of forming a bottom electrode comprises:

depositing a noble metal over said relatively thick oxide layer, said first spacers and said titanium aluminum nitride layer; and

removing said noble metal from said relatively thick oxide layer and said first spacers except for over said titanium aluminum nitride layer and laterally thereof in contact with said first spacers.

34. The method of claim 33 wherein said noble metal comprises one of Ir, IrOx, Pt, Pd, PdOx, Ru, RuOx, Rh, or RhOx.

35. The method of claim 33 wherein said step of removing comprises a wet etch process.

36. The method of claim 27 wherein said step of depositing, planarizing and selectively removing an oxide material comprises:

depositing said oxide material over said relatively thick oxide layer, said first spacers and said bottom electrode in said opening;

chemical mechanical polishing of said oxide material to a level of said first spacers; and

removing said oxide material within said opening to a level of said bottom electrode except adjoining said first spacers to form said additional oxide layer adjoining said first spacers.

37. The method of claim 27 wherein said step of depositing and selectively etching a second aluminum oxide layer comprises:

chemical vapor deposition of aluminum oxide over said relatively thick oxide layer, said additional oxide layer adjoining said first spacers and said bottom electrode; and

removal of said aluminum oxide from said relatively thick oxide layer and upper portions of said additional oxide material and said bottom electrode to form said second spacers medially displaced from said first spacers.

38. The method of claim 37 wherein said step of removal of said aluminum oxide comprises a directional reactive ion etch process.

39. The method of claim 27 wherein said step of depositing and etching a ferroelectric layer comprises:

depositing a ferroelectric material on said bottom electrode between said second spacers; and

removing a portion of said ferroelectric material to a level below distal ends of said second spacers.

40. The method of claim 39 wherein said ferroelectric material comprises one of PZT, PLZT, BST, SBT, STO or other ferroelectric dielectric materials.

41. The method of claim 27 wherein said step of forming a top electrode comprises:

depositing a noble metal over said ferroelectric layer; and

etching said noble metal to a level below distal ends of said second spacers.

42. The method of claim 41 wherein said noble metal comprise one of Ir, IrOx, Pt, Pd, PdOx, Ru, RuOx, Rh, or RhOx.

43. The method of claim 41 further comprising:

also depositing a Ti/TIN layer over said noble metal; and

etching said Ti/TiN layer to a level below distal ends of said second spacers.

44. The method of claim 27 wherein said step of forming a Ti/TiN and W contact comprises:

depositing a nitride layer over said top electrode;

planarizing said nitride layer to a level of said relatively thick oxide layer;

etching through a portion of said additional oxide layer to form a bottom electrode contact opening; and

etching through said nitride layer to form a top electrode contact opening.

45. The method of claim 42 wherein said steps of forming said contact to said bottom electrode and forming said contact to said top electrode comprise:

depositing Ti/TiN liners in said bottom electrode contact opening and said top electrode contact opening;

and chemical vapor depositing W in said Ti/TiN liners.

46. The method of claim 27 further comprising:

planarizing said contacts to said bottom and top electrodes to a level of said relatively thick oxide layer.

47. The method of claim 46 wherein said step of planarizing comprises a chemical mechanical polishing process.

48. A method for forming an integrated circuit device on a substrate including at least one contact stud, said method comprising:

forming a first insulating layer on said substrate;

removing a portion of said first insulating layer to produce an opening to an exposed surface of said substrate therein;

forming first spacers on sidewalls of said opening;

forming a first conductive layer in contact with said at least one contact stud on said exposed surface of said substrate separated from said first spacers on said sidewalls of said opening by a gap therebetween;

forming a bottom electrode of a ferroelectric capacitor over said first conductive layer and in said gap laterally of said first conductive layer;

forming a second insulating layer adjoining said spacers in said opening;

forming second spacers on said second insulating layer in said opening;

forming a ferroelectric dielectric on said bottom electrode between said second spacers;

forming a top electrode on said ferroelectric dielectric; and

forming an electrical contact to said top electrode.

49. The method of claim 48 wherein said step of forming first spacers on said sidewalls of said opening comprises:

depositing a first spacer material over said first insulating layer; and

removing said first spacer material except on said sidewalls of said opening.

50. The method of claim 49 wherein said first spacer material comprises Al 2 O 3 .

51. The method of claim 49 wherein said step of depositing is carried out by chemical vapor deposition.

52. The method of claim 48 wherein said step of forming said first conductive layer comprises:

depositing a first conductive layer material over said first insulating layer and said first spacers in contact with said at least one contact stud; and

removing said first conductive layer material except on said exposed surface of said substrate separated from said first spacers by said gap.

53. The method of claim 52 wherein said first conductive layer material comprises titanium aluminum nitride.

54. The method of claim 52 wherein said step of depositing is carried out by chemical vapor deposition.

55. The method of claim 48 wherein said step of forming said bottom electrode comprises:

depositing a bottom electrode material over said first insulating layer, said first spacers and in said gap laterally of said first conductive layer in said opening; and

removing said bottom electrode material except over said bottom electrode and within said gap.

56. The method of claim 55 wherein said bottom electrode material comprises Pt.

57. The method of claim 55 wherein said step of depositing comprises chemical vapor deposition.

58. The method of claim 48 wherein said step of forming said second insulating layer comprises:

depositing an oxide over said first insulating layer, said first spacers and said bottom electrode;

and removing said oxide except adjoining said first spacers.

59. The method of claim 48 wherein said step of forming said second spacers comprises:

depositing a second spacer material over said first and second insulating layers and said bottom electrode;

and removing said second spacer material except adjoining said second insulting layer in said opening.

60. The method of claim 59 wherein said second spacer material comprises Al 2 O 3 .

61. The method of claim 59 wherein said step of depositing comprises chemical vapor deposition.

62. The method of claim 48 wherein said step of forming said ferroelectric dielectric comprises:

depositing said ferroelectric dielectric material over said bottom electrode; and

annealing said ferroelectric dielectric material.

63. The method of claim 62 wherein said step of depositing is carried out by deposition of one of PZT, PLZT, BST, SBT, STO or other ferroelectric dielectric materials.

64. The method of claim 48 wherein said step of forming said top electrode comprises:

depositing a top electrode material over said ferroelectric dielectric.

65. The method of claim 64 wherein said top electrode material comprises one of Ir, IrOx, Pt, Pd, PdOx, Ru, RuOx, Rh, RhOx, or other compatible noble metals.

66. The method of claim 48 further comprising:

forming a contact layer material over said top electrode.

67. The method of claim 66 wherein said step of forming said contact layer material is carried out by the deposition of Ti/TiN.

68. The method of claim 48 wherein said step of forming said electrical contact comprises:

depositing a conductive layer material over said top electrode.

69. The method of claim 68 wherein said step of depositing comprises the steps of:

firstly depositing a first contact material over said top electrode; and

secondly depositing said conductive layer material over said first contact material.

70. The method of claim 69 wherein said first contact material comprises Ti/TiN and said conductive layer material comprises W.

71. The method of claim 69 wherein said conductive layer material is deposited by chemical vapor deposition.

Assignments (7)