Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) with simultaneous formation of sidewall ferroelectric capacitors

1. A method for forming a semiconductor device on a substrate having at least two contact studs formed in a planar surface thereof, the method comprising:

forming an insulating layer overlying said planar surface;

selectively removing a portion of said insulating layer and a selected portion of said planar surface to form an opening extending to and partially between said at least two contact studs;

forming first spacers adjoining sides of said opening over said at least two contact studs;

forming bottom electrode spacers, each contacting respective ones of said at least two contact studs in said opening adjoining said first spacers;

forming an insulating cap in said opening between said at least two contact studs and said bottom electrode spacers;

forming a ferroelectric dielectric layer in said opening over said insulating layer, said insulating cap and between said bottom electrode spacers;

forming a pair of top electrodes within said opening comprising first and second side portions displaced laterally from respective ones of said bottom electrode spacers by said ferroelectric dielectric layer;

forming an additional insulating layer between said top electrodes and over said ferroelectric dielectric layer; and

forming first and second contacts to respective ones of said pair of top electrodes within said additional insulating layer.

2. The method of claim 1 wherein said step of forming an insulating layer comprises:

depositing oxide on said planar surface.

3. The method of claim 1 wherein said step of selectively removing a portion of said insulating layer and a selected portion of said planar surface comprises:

patterning a mask on said insulating layer; and

etching said insulating layer and said selected portion of said planar surface in areas defined by said mask.

4. The method of claim 3 wherein said mask comprises one of Al 2 O 3 or Si 3 N 4 .

5. The method of claim 3 wherein said step of etching comprises reactive ion etching.

6. The method of claim 1 wherein said step of forming first spacers comprises:

depositing a layer of titanium aluminum nitride in said opening; and

removing said titanium aluminum nitride except for sidewalls of said opening.

7. The method of claim 6 wherein said step of forming bottom electrode spacers comprises:

depositing a bottom electrode layer comprising at least one of Pt, Ir, IrOx, Pd, PdOx, Ru, RuOx, Rh, RhOx or other noble metal on said titanium aluminum nitride in said opening; and

removing said bottom electrode layer except for portions adjoining said first spacers.

8. The method of claim 1 wherein said step of forming an insulating cap comprises:

depositing an oxide layer in said opening between said first and bottom electrode spacers; and

removing said oxide layer except for a lower portion of said opening.

9. The method of claim 1 wherein said step of forming a ferroelectric dielectric layer comprises:

depositing a ferroelectric material comprising at least one of PZT, PLZT, BST, SBT or STO.

10. The method of claim 1 wherein said step of forming said pair of top electrodes comprises:

depositing a top electrode layer comprising at least one of Pt, Ir, IrOx, Pd, PdOx, Ru, RuOx, Rh, RhOx or other noble metal over said ferroelectric dielectric layer; and

removing said top electrode layer except for portions aligned with sidewalls of said opening and displaced from said bottom electrode spacers by said ferroelectric dielectric layer.

11. The method of claim 1 wherein said step of forming an additional insulating layer comprises:

depositing an oxide between said top electrodes and over said ferroelectric dielectric layer.

12. The method of claim 11 further comprising:

planarizing said oxide.

13. The method of claim 12 wherein said step of planarizing comprises CMP.

14. The method of claim 1 wherein said step of forming first and second contacts to said top electrode comprises:

selectively etching said additional insulating layer in a pattern defined by a photoresist mask to produce first and second contact openings; and

producing a contact in each of said first and second contact openings.

15. The method of claim 14 wherein said step of producing said contact comprises:

depositing Ti/TiN liners in said first and second contact openings; and

depositing W in said Ti/TiN liners.

16. The method of claim 1 further comprising:

planarizing said first and second contacts to a level of said additional insulating layer.

17. The method of claim 16 wherein said step of planarizing comprises CMP.

18. A method for forming a ferroelectric device comprising:

forming first and second contact studs in a planar surface of a substrate;

depositing an oxide layer on said planar surface;

selectively etching said oxide layer to form an opening through said oxide layer to said first and second contact studs and an over-etched region therebetween;

depositing a titanium aluminum nitride layer over said oxide layer and within said opening and over-etched region;

selectively removing portions of said titanium aluminum nitride layer except for sidewalls of said opening adjoining said first and second contact studs to produce first spacers;

depositing a noble metal layer within said opening;

selectively removing said noble metal layer over said first and second contact studs and within said over-etched region to produce bottom electrode spacers medially of said first spacers;

depositing an additional oxide layer within said opening;

selectively removing said additional oxide layer to produce a trench cap in a lower portion of said opening and within said over-etched region;

depositing a ferroelectric dielectric layer over said oxide layer, said trench cap and medial and distal portions of said first and bottom electrode spacers within said opening;

depositing an additional noble metal layer over said ferroelectric dielectric layer;

selectively removing said additional noble metal layer to form a pair of top electrodes within said opening displaced from said bottom electrode spacers by said ferroelectric dielectric layer;

depositing a further oxide layer over said ferroelectric dielectric layer and between said pair of top electrodes;

selectively etching said further oxide layer to form first and second openings to corresponding first and second ones of said top electrodes; and

forming electrical contacts to said first and second ones of said top electrodes through said first and second openings.

19. The method of claim 18 wherein said step of selectively etching said oxide layer comprises:

patterning a mask on said oxide layer; and

etching said oxide layer and said planar surface between said first and second contact studs to produce said opening and said over-etched region.

20. The method of claim 19 wherein said mask comprises Al 2 O 3 or Si 3 N 4 .

21. The method of claim 19 wherein said step of etching said oxide layer comprises reactive ion etching.

22. The method of claim 18 wherein said step of depositing a noble metal layer comprises:

depositing at least one of Pt, Ir, IrOx, Pd, PdOx, Ru, RuOx, Rh, RhOx or other noble metal in said opening.

23. The method of claim 18 wherein said step of depositing a ferroelectric dielectric layer comprises:

depositing at least one of PZT, PLZT, BST, SBT or STO.

24. The method of claim 18 wherein said step of depositing an additional noble metal layer comprises:

depositing at least one of Pt, Ir, IrOx, Pd, PdOx, Ru, RuOx, Rh, RhOx or other noble metal over said ferroelectric dielectric layer.

25. The method of claim 18 wherein said step of depositing an additional oxide layer further comprises:

planarizing said additional oxide layer.

26. The method of claim 18 wherein said step of selectively etching said additional oxide layer comprises:

selectively etching said additional oxide layer in a pattern defined by a photoresist mask to produce said first and second openings.

27. The method of claim 18 wherein said step of forming electrical contacts comprises:

depositing Ti/TiN liners in said first and second openings; and

depositing W in said Ti/TiN liners.

28. The method of claim 18 further comprising:

planarizing said electrical contacts to a level of said additional oxide layer.

29. The method of claim 28 wherein said step of planarizing comprises a CMP operation.

30. The method of claim 18 further comprising:

additionally forming an electrical contact to a third contact stud in said planar surface of said substrate through a third opening through said additional oxide layer, said ferroelectric dielectric layer and said oxide layer substantially concurrently with said step of forming said electrical contacts to said first and second ones of said top electrodes.