Semiconductor memory including switching circuit for selecting data supply
A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.
1. A semiconductor memory, comprising:
a first output buffer corresponding to a first pad;
a second output buffer corresponding to a second pad; and
a switch circuit that performs one selected function from a group consisting of supplying first data from a first data line to the first output buffer and the second output buffer and supplying second data from a second data line which is different from the first data line to the second output buffer while supplying the first data to the first output buffer.
2. The semiconductor memory according to claim 1 , wherein the switch circuit is supplied with information indicating a bus width of the memory.
3. The semiconductor memory according to claim 1 , further comprising a bus having an n-bit width for outputting data, wherein n is a positive integer, and a total number of the first pad and the second pad is 2n.
4. The semiconductor memory according to claim 2 , wherein the number of the first pad is n and the number of the second pad is n.
5. The semiconductor memory according to claim 1 , further comprising:
a first circuit including a first column decoder; and
a second circuit including a second column decoder,
wherein the switch circuit is included to the first circuit and the second circuit.
6. The semiconductor memory according to claim 5 , further comprising:
a first signal line coupled to the first output buffer;
a second signal line coupled to the second output buffer;
a third signal line coupled to the first circuit and the first signal line;
a fourth signal line coupled to the first circuit and the second signal line;
a fifth signal line coupled to the second circuit and the first signal line; and
a sixth signal line coupled to the second circuit and the second signal line.
7. The semiconductor memory according to claim 1 , further comprising:
a first circuit including a first column decoder;
a second circuit including a first column decoder;
a first signal line coupled to the first output buffer;
a second signal line coupled to the second output buffer;
a third signal line coupled to the first circuit; and
a fourth signal line coupled to the second circuit,
wherein the switch circuit comprises:
a first switch circuit that selectively couples one of the third signal line and the fourth signal line to the first signal line; and
a second switch circuit that selectively couples one of the third signal line and the fourth signal line to the second signal line.