Analog-to-digital converter and wireless receiver
The influence of a jitter of a sampling clock of an analog-to-digital converter is digitally corrected at low power consumption. The sampling clock of the analog-to-digital converter is generated by a phase locked loop (PLL) using a reference clock, which has a lower frequency and lower jitter than the sampling clock, as a source oscillation. A time-to-digital converter (TDC) converts a timing error at a timing where the sampling clock and the reference clock are synchronized with each other into a digital value. A timing error at a sampling timing where the reference clock is not present is generated by interpolating a detected timing error. Thus, a jitter value of the sampling clock at each sampling timing is obtained. A sampling voltage error is calculated from the jitter value and the output of the analog-to-digital converter is digitally corrected.
1. An analog-to-digital converter for sampling an input analog voltage and converting the input analog voltage into a digital value, comprising:
a phase locked loop that uses a reference clock as a source oscillation, has a higher frequency than the reference clock, and generates a sampling clock synchronizing with the reference clock;
an analog-to-digital conversion unit that samples the input analog voltage using the sampling clock and converts the input analog voltage into a digital value;
a time-to-digital converter that detects a time difference between a voltage transition timing of the reference clock and a voltage transition timing of the sampling clock and converts the time difference into a differential digital value; and
a digital correction unit that interpolates the differential digital value to obtain an interpolation value corresponding to each sampling timing and digitally corrects influence of jitter of the sampling clock included in a raw digital output of the analog-to-digital conversion unit by the interpolation value.
2. The analog-to-digital converter according to claim 1 , wherein
the digital correction unit obtains a differential value of the raw digital output of the analog-to-digital conversion unit and digitally corrects the raw digital output based on the differential value and the interpolation value.
3. An analog-to-digital converter for sampling an input analog voltage and converting the input analog voltage into a digital value, comprising:
a plurality of analog-to-digital conversion units that sample the input analog voltage using a plurality of corresponding first sampling clocks having the same frequency and different phases from each other;
a plurality of time-to-digital converters provided corresponding to the analog-to-digital conversion units for detecting a time difference between a voltage transition timing of a reference clock and a voltage transition timing of the first sampling clock and converting the time difference into a differential digital value; and
a plurality of digital correction units provided corresponding to the analog-to-digital conversion units for interpolating the differential digital value to obtain an interpolation value corresponding to each sampling timing and digitally correcting influence of jitter of the first sampling clock included in a raw digital output of the corresponding analog-to-digital conversion unit by the interpolation value.
4. The analog-to-digital converter according to claim 3 , further comprising:
a reference analog-to-digital converter; and
a skew retrieval unit, wherein
the reference analog-to-digital converter samples the input analog voltage by a plurality of first sampling clocks corresponding to the analog-to-digital conversion units and a second sampling clock having a frequency sequentially synchronizing with the sampling timings, and generates a reference digital value,
the skew retrieval unit retrieves a sampling timing skew included in each of the plurality of first sampling clocks, and supplies the obtained sampling timing skew to the digital correction units, and
the plurality of digital correction units digitally correct influence of jitter and skew of the first sampling clocks included in the raw digital output of the corresponding analog-to-digital conversion unit based on the corresponding interpolation value and the sampling timing skew.
5. The analog-to-digital converter according to claim 3 , wherein
the plurality of first sampling clocks are generated by dividing a third sampling clock synchronizing with a reference clock generated by a phase locked loop using the reference clock, whose frequency is lower than that of the first sampling clocks, as a source oscillation.
6. The analog-to-digital converter according to claim 4 , wherein
the plurality of first sampling clocks are generated by dividing a fourth sampling clock synchronizing with a reference clock generated by a phase locked loop using the reference clock, whose frequency is lower than that of the first sampling clocks, as a source oscillation.
7. The analog-to-digital converter according to claim 3 , wherein
each of the plurality of digital correction units obtains a differential value of the raw digital output of the corresponding analog-to-digital conversion unit and digitally corrects the raw digital output based on the differential value and the corresponding interpolation value.
8. The analog-to-digital converter according to claim 4 , wherein
each of the plurality of digital correction units obtains a differential value of the raw digital output of the corresponding analog-to-digital conversion unit and digitally corrects the raw digital output based on the differential value and the corresponding interpolation value.
9. The analog-to-digital converter according to claim 5 , wherein
each of the plurality of digital correction units obtains a differential value of the raw digital output of the corresponding analog-to-digital conversion unit and digitally corrects the raw digital output based on the differential value and the corresponding interpolation value.
10. The analog-to-digital converter according to claim 6 , wherein
each of the plurality of digital correction units obtains a differential value of the raw digital output of the corresponding analog-to-digital conversion unit and digitally corrects the raw digital output based on the differential value and the corresponding interpolation value.
11. The analog-to-digital converter according to claim 3 , wherein
the first sampling clocks corresponding to the plurality of analog-to-digital conversion units are generated by extracting a harmonic wave included in the reference clock or a division output thereof by filtering, and dividing the extracted harmonic wave.
12. The analog-to-digital converter according to claim 4 , wherein
the first sampling clocks corresponding to the plurality of analog-to-digital conversion units are generated by extracting a harmonic wave included in the reference clock or a division output thereof by filtering, and dividing the extracted harmonic wave.
13. The analog-to-digital converter according to claim 3 , wherein
the plurality of first sampling clocks corresponding to the plurality of analog-to-digital conversion units are generated by injecting the reference clock or a division output thereof into an injection locking oscillator, dividing an oscillation output of the injection locking oscillator, and using an obtained division output.
14. The analog-to-digital converter according to claim 4 , wherein
the plurality of first sampling clocks corresponding to the plurality of analog-to-digital conversion units are generated by injecting the reference clock or a division output thereof into an injection locking oscillator, dividing an oscillation output of the injection locking oscillator, and using an obtained division output.
15. A wireless receiver, comprising:
a reception circuit unit for receiving a wireless signal, the reception circuit having an analog-to-digital converter including a phase locked loop that uses a reference clock as a source oscillation, has a higher frequency than the reference clock and generates a sampling clock synchronizing with the reference clock,
an analog-to-digital conversion unit that samples an input analog voltage using the sampling clock and converts the input analog voltage into a digital value,
a time-to-digital converter that detects a time difference between a voltage transition timing of the reference clock and a voltage transition timing of the sampling clock and converts the time difference into a differential digital value,
and a digital correction unit that interpolates the differential digital value to obtain an interpolation value corresponding to each sampling timing and digitally corrects influence of jitter of the sampling clock included in a raw digital output of the analog-to-digital conversion unit by the interpolation value; and
a phase locked loop that generates a local oscillation signal for converting a frequency of the wireless signal.