Memory array including magnetic random access memory cells and oblique field lines
View Patent ↗A memory device includes a first plurality of magnetic random access memory (MRAM) cells positioned along a first direction, and a first bit line electrically connected to the first plurality of MRAM cells, the bit line oriented in the first direction. The device includes a first plurality of field lines oriented in a second direction different from the first direction, the first plurality of field lines being spaced such that only a corresponding first one of the first plurality of MRAM cells is configurable by each of the first plurality of field lines. The device includes a second plurality of field lines oriented in a third direction different from the first direction and the second direction, the second plurality of field lines being spaced such that only a corresponding second one of the first plurality of MRAM cells is configurable by each of the second plurality of field lines.
1. A memory device comprising:
a first plurality of magnetic random access memory (MRAM) cells positioned along a first direction;
a first bit line electrically connected to the first plurality of MRAM cells, the first bit line oriented in the first direction;
a first plurality of field lines oriented in a second direction different from the first direction, the first plurality of field lines being spaced such that only a corresponding first one of the first plurality of MRAM cells is configurable by each of the first plurality of field lines; and
a second plurality of field lines oriented in a third direction different from the first direction and the second direction, the second plurality of field lines being spaced such that only a corresponding second one of the first plurality of MRAM cells is configurable by each of the second plurality of field lines;
wherein in a first mode, a magnetization direction associated with each of the first plurality of MRAM cells is settable by either of a first current flowing through one of the first plurality of field lines or a second current flowing through one of the second plurality of field lines; and
wherein in a second mode, the magnetization direction associated with each of the first plurality of MRAM cells is settable by both the first current and the second current applied concurrently.
2. The memory device of claim 1 , wherein the second direction is orthogonal to the third direction.
3. The memory device of claim 1 , wherein:
each of the first plurality of field lines is magnetically isolated from the first plurality of MRAM cells except for the corresponding first one of the first plurality of MRAM cells; and
each of the second plurality of field lines is magnetically isolated from the first plurality of MRAM cells except for the corresponding second one of the first plurality of MRAM cells.
4. The memory device of claim 1 , further comprising:
a second plurality of magnetic random access memory (MRAM) cells positioned along the first direction, wherein the second plurality of MRAM cells is spaced apart from the first plurality of MRAM cells in a fourth direction orthogonal to the first direction; and
a second bit line electrically connected to the first plurality of MRAM cells, the second bit line oriented in the first direction;
wherein the first plurality of field lines is spaced such that only a corresponding first one of the second plurality of MRAM cells is configurable by each of the first plurality of field lines; and
wherein the second plurality of field lines is spaced such that only a corresponding second one of the second plurality of MRAM cells is configurable by each of the second plurality of field lines.
5. The memory device of claim 1 , wherein a first one of the first plurality of MRAM cells includes a first storage layer having a magnetization direction that is switchable to store data corresponding to one of at least three logic states.
6. The memory device of claim 5 , wherein a second one of the first plurality of MRAM cells includes a second storage layer having a magnetization direction that is switchable to store data corresponding to one of two logic states.
7. The memory device of claim 1 , wherein the first plurality of MRAM cells are connected in series to produce a combined output.
8. The memory device of claim 1 , wherein at least one of the first plurality of MRAM cells is self-referenced.
9. The memory device of claim 1 , wherein an angle between the second direction and the third direction is in the range from 5 degrees to 85 degrees.
10. The memory device of claim 1 , wherein the first plurality of MRAM cells includes at least one multi-bit stacked MRAM cell and at least one multi-bit unstacked MRAM cell.
11. A memory array comprising:
a plurality of columns of magnetic random access memory (MRAM) cells, each of the plurality of columns being oriented in a first direction and being electrically connected to a corresponding bit line oriented in the first direction;
a first plurality of field lines oriented in a second direction different from the first direction; and
a second plurality of field lines oriented in a third direction different from the first direction and the second direction;
wherein each of the MRAM cells is configurable by a corresponding one of the first plurality of field lines and a corresponding one of the second plurality of field lines, and each of the MRAM cells is magnetically isolated from each remaining one of the first plurality of field lines and each remaining one of the second plurality of field lines;
wherein in a first mode, a magnetization direction associated with each of the MRAM cells is settable by either of a first current flowing through one of the first plurality of field lines or a second current flowing through one of the second plurality of field lines; and
wherein in a second mode, the magnetization direction associated with each of the MRAM cells is settable by both the first current and the second current applied concurrently.
12. The memory array of claim 11 , wherein the second direction is orthogonal to the third direction.
13. The memory array of claim 11 , wherein an angle between the second direction and the third direction is in the range from 5 degrees to 85 degrees.
14. The memory array of claim 11 , wherein a first MRAM cell included in the plurality of columns of MRAM cells includes a first storage layer having a magnetization direction that is switchable to store data corresponding to one of at least three logic states.
15. The memory array of claim 11 , wherein a second MRAM cell included in the plurality of columns of MRAM cells includes a second storage layer having a magnetization direction that is switchable to store data corresponding to one of two logic states.
16. The memory array of claim 11 , wherein at least one of the plurality of columns of MRAM cells are connected in series to produce a combined output.
17. The memory array of claim 11 , wherein at least one MRAM cell included in the plurality of columns of MRAM cells is self-referenced.
18. The memory array of claim 11 , wherein the first plurality of field lines and the second plurality of field lines are oriented and spaced such that a single selected MRAM cell included in each of the plurality of columns of MRAM cells is readable without affecting values of the resistances of each remaining unselected MRAM cell in the each of the plurality of columns of MRAM cells.
19. The memory array of claim 11 , wherein at least one multi-bit stacked MRAM cell and at least one multi-bit unstacked MRAM cell are included in the plurality of columns of MRAM cells.
20. The memory array of claim 11 , wherein the first plurality of field lines and the second plurality of field lines are oriented at an angle of 45 degrees relative to the plurality of columns of MRAM cells, such that power efficiency of configuring stored and sense magnetizations of the MRAM cells is maximized.