IP Library › Granted Patent US 8,766,275
Granted Patent B2
US 8,766,275 · App. 13/574,993 · Granted Jul 1, 2014

Composite semiconductor device

Inventors: Naoyasu Iketani (Osaka, JP); Tomohiro Nozawa (Osaka, JP); Yoshiaki Nozaki (Osaka, JP); John K. Twynam (Osaka, JP); Hiroshi Kawamura (Osaka, JP); Keiichi Sakuno (Osaka, JP)
Assignee: Sharp Kabushiki Kaisha
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Quick Facts
Patent No.
US 8,766,275
App. No.
13/574,993
Granted
Jul 1, 2014
Kind
B2
Abstract

This composite semiconductor device has a normally-on first field effect transistor and a normally-off second field effect transistor connected in series between first and second terminals, gates of the first and second field effect transistors being connected to second and third terminals, respectively, and N diodes being connected in series in a forward direction between a drain and a source of the second field effect transistor. Therefore, a drain-source voltage (Vds) of the second field effect transistor can be restricted to a voltage not higher than a withstand voltage of the second field effect transistor.

Claims (34)

1. A composite semiconductor device, comprising:

a first terminal receiving a first voltage;

a second terminal receiving a second voltage lower than said first voltage;

a third terminal selectively provided with any one of a third voltage and a fourth voltage higher than the third voltage;

a normally-on first field effect transistor having a drain connected to said first terminal and a gate connected to said second terminal;

a normally-off second field effect transistor having a drain connected to a source of said first field effect transistor, a source connected to said second terminal, and a gate connected to said third terminal, rendered non-conductive when said third voltage is provided to said third terminal, and rendered conductive when said fourth voltage is provided to said third terminal; and

a protection circuit connected in parallel to said second field effect transistor, for protecting said second field effect transistor by maintaining a voltage across the drain and the source of said second field effect transistor to a voltage not higher than a withstand voltage of said second field effect transistor,

said protection circuit including N (N being a natural number) unipolar rectifier elements connected in series between the drain and the source of said second field effect transistor in a forward direction and rendered conductive when a voltage across the drain and the source of said second field effect transistor exceeds a predetermined voltage not higher than a withstand voltage of said second field effect transistor.

2. The composite semiconductor device according to claim 1 , wherein in a case where a voltage of said third terminal varies from said fourth voltage to said third voltage, a time period from start of increase in voltage across the drain and the source of said second field effect transistor until conduction of said N unipolar rectifier elements is set to at most half a time period from start of increase in voltage across the drain and the source of said second field effect transistor until non-conduction of said first field effect transistor.

3. The composite semiconductor device according to claim 1 , wherein each of said N unipolar rectifier elements is a Schottky diode.

4. The composite semiconductor device according to claim 3 , wherein each of said N unipolar rectifier elements is formed of a material greater in energy band gap than Si.

5. The composite semiconductor device according to claim 4 , wherein said material is AlxGa{tilde over (1)}xN (0≦x≦1), SiC, diamond, AlxGa{tilde over (1)}xAs (0≦x≦1), InxGa{tilde over (1)}xP (0≦x≦1), or AlxInyGa{tilde over (1)}{tilde over (x)}yN (0≦x≦1, 0≦y≦1, 0≦x+y≦1).

6. The composite semiconductor device according to claim 3 , comprising a first semiconductor chip including first and second nitride-based semiconductor layers successively stacked on a first semiconductor substrate, wherein said N Schottky diodes are formed in N regions on a surface of said first semiconductor chip, respectively,

an anode electrode and a cathode electrode of a corresponding Schottky diode are provided at a distance from each other in each region,

a recess portion penetrating said second nitride-based semiconductor layer and reaching said first nitride-based semiconductor layer is formed in each region,

said anode electrode is formed in said recess portion, and

said cathode electrode is formed on a surface of said second nitride-based semiconductor layer.

7. The composite semiconductor device according to claim 6 , comprising a second semiconductor chip including third and fourth nitride-based semiconductor layers successively stacked on a second semiconductor substrate, wherein

said first field effect transistor is formed on a surface of said second semiconductor chip,

a gate electrode, a source electrode, and a drain electrode of said first field effect transistor are formed on a surface of said fourth nitride-based semiconductor layer, and

the gate electrode is provided between the source electrode and the drain electrode.

8. The composite semiconductor device according to claim 7 , wherein said third nitride-based semiconductor layer is formed of GaN, and said fourth nitride-based semiconductor layer is formed of AlxGa{tilde over (1)}xN (0<x≦1).

9. The composite semiconductor device according to claim 3 , comprising a semiconductor chip including first and second nitride-based semiconductor layers successively stacked on a semiconductor substrate, wherein

said N Schottky diodes are formed in N first regions on a surface of the semiconductor chip, respectively,

said first field effect transistor is formed in a second region on the surface of said semiconductor chip,

an anode electrode and a cathode electrode of a corresponding Schottky diode are provided at a distance from each other in each first region,

a recess portion penetrating said second nitride-based semiconductor layer and reaching said first nitride-based semiconductor layer is formed in each first region,

said anode electrode is formed in said recess portion,

said cathode electrode is formed on a surface of said second nitride-based semiconductor layer,

a gate electrode, a source electrode, and a drain electrode of said first field effect transistor are formed on the surface of said second nitride-based semiconductor layer in said second region, and

the gate electrode is provided between the source electrode and the drain electrode.

10. The composite semiconductor device according to claim 9 , wherein said first nitride-based semiconductor layer is formed of GaN, and said second nitride-based semiconductor layer is formed of AlxGa{tilde over (1)}xN (0<x≦1).

11. The composite semiconductor device according to claim 1 , further comprising a first resistor element interposed between the gate of said first field effect transistor and said second terminal.

12. The composite semiconductor device according to claim 1 , further comprising a second resistor element interposed between said first terminal and the drain of said first field effect transistor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2019
From: SHARP KABUSHIKI KAISHA
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 049403/0835 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2012
From: IKETANI, NAOYASU; NOZAWA, TOMOHIRO; NOZAKI, YOSHIAKI; TWYNAM, JOHN K.; KAWAMURA, HIROSHI; SAKUNO, KEIICHI
To: SHARP KABUSHIKI KAISHA
Reel/Frame 028647/0299 →
Priority Claims (2)
JP 2010-013083 · Jan 25, 2010 · national
JP 2010-182165 · Aug 17, 2010 · national
Continuity (1)
Related Publication 20120292635A1 · Nov 22, 2012