Broadband analog radio-frequency integrator
Broadband analog radio-frequency devices can be used to create building blocks for scalable analog signal processors that operate over bandwidths of 50 MHz to 20 GHz or more. Example devices include integrators (transconductors), digitally controlled attenuators, buffers, and scalable summers implemented using deep sub-micron CMOS technology. Because the devices are implemented in CMOS, the ratio of trace/component size to signal wavelength is about the same as that of low-frequency devices implemented in printed circuit boards. Combining this scaling with high gain/high bandwidth enables implementation of feedback and programmability for broadband analog signal processing.
1. A broadband analog radio-frequency integrator comprising:
first and second p-channel transistors including respective sources coupled in parallel to a first voltage supply terminal and respective drains configured to provide complementary output signals;
first and second variable resistors including respective first terminals coupled to the drains of the first and second p-channel transistors, respectively, and respective second terminals coupled to gates of the second and first p-channel transistors, respectively; and
first and second n-channel transistors including respective drains coupled to the second terminals of the first and second variable resistors, respectively, respective gates configured to receive complementary input signals, and respective sources in electrical communication with a second voltage supply terminal.
2. The integrator of claim 1 , further including a bias transistor connected in series between the second voltage supply terminal and the sources of the first and second re-channel transistors.
3. The integrator of claim 1 , wherein the first and second variable resistors include third and fourth n-channel transistors, respectively, and further including a third voltage supply terminal in electrical communication with the gates of the third and fourth n-channel transistors, the third voltage supply configured to control resistance of the first and second variable resistors.
4. The integrator of claim 1 , wherein the integrator is fabricated using deep sub-micron complementary-metal-oxide-semiconductor, silicon germanium, or silicon-on-insulator techniques.
5. The integrator of claim 1 , wherein the transistors are interleaved with each other to reduce bias offset.
6. The integrator of claim 1 , further comprising a tuning circuit configured to adjust sampling of an output of the integrator.
7. The integrator of claim 6 , wherein the tuning circuit further comprises a DC calibration circuit and a gain control circuit.
8. The integrator of claim 1 , wherein the first and second variable resistors include third and fourth n-channel transistors, respectively, the third and fourth n-channel transistors including respective drains coupled to the drains of the first and second p-channel transistors, respectively, respective sources coupled to gates of the second and first p-channel transistors, respectively, and respective gates coupled to each other.