Data storing devices and methods of fabricating the same
A data storing device may include a substrate, transistors on the substrate that include gate line structures, and conductive isolation patterns defining active regions of the transistors. Each conductive isolation pattern includes at least one portion buried in the substrate and the conductive isolation patterns are electrically connected with each other.
1. A data storing device, comprising:
a substrate;
transistors on the substrate, the transistors including gate line structures and second source/drain regions in the substrate between the gate line structures; and
conductive isolation patterns defining active regions of the transistors, each conductive isolation pattern including at least one portion buried in the substrate, and the conductive isolation patterns being electrically connected with each other, wherein source lines are disposed on the second source/drain regions and extend along the gate line structures.
2. The device as claimed in claim 1 , wherein:
each of the gate line structures includes at least one portion buried in the substrate, and
the conductive isolation patterns extend substantially parallel to the gate line structures.
3. The device as claimed in claim 2 , wherein:
each of the conductive isolation patterns and the gate line structures includes an insulating layer, a conductive line, and a capping pattern that are sequentially stacked on the substrate, and
the conductive line is electrically isolated from the substrate by the insulating layer and the capping pattern.
4. The device as claimed in claim 3 , wherein, in each of the conductive isolation patterns and the gate line structures, an uppermost surface of the conductive line is lower than an uppermost surface of the substrate.
5. The device as claimed in claim 2 , wherein the gate line structures are provided in first trenches within the substrate and the conductive isolation patterns are provided in second trenches within the substrate, the first trenches and the second trenches having substantially same depths.
6. The device as claimed in claim 1 , further comprising a conductive connecting pattern electrically connecting the conductive isolation patterns with each other, the conductive connecting pattern extending along a direction that crosses the gate line structures.
7. The device as claimed in claim 1 , wherein the conductive isolation patterns reduce formation of a channel region in regions of the substrate under the conductive isolation patterns, during an operation of the data storing device.
8. The device as claimed in claim 1 , wherein the conductive isolation patterns are configured to receive a ground or negative voltage, during an operation of the data storing device.
9. The device as claimed in claim 1 , wherein the conductive isolation patterns are configured to have applied thereto a same voltage as that applied to unselected gate line structures of the gate line structures, during reading and writing operations of the data storing device.
10. The device as claimed in claim 1 wherein:
the transistors further include:
first source/drain regions spaced apart from the second source/drain regions by the gate line structures.
11. The device as claimed in claim 10 , further comprising a source connecting line electrically connecting the source lines with each other.
12. The device as claimed in claim 10 , wherein the gate line structures include conductive lines, respectively, and lowermost surfaces of the source lines are higher than uppermost surfaces of the conductive lines.
13. The device as claimed in claim 10 , further comprising device isolation layers crossing the gate line structures and defining the active regions of the transistors, the second source/drain regions being spaced apart from each other by the device isolation layers in a direction parallel to the gate line structures.
14. The device as claimed in claim 10 , wherein each of the source lines includes:
a first conductive pattern in contact with the one of the second source/drain regions, the first conductive pattern including a semiconductor material, and
a second conductive pattern on the first conductive pattern, the second conductive pattern including a metallic material.
15. The device as claimed in claim 10 , further comprising variable resistance structures, each of the variable resistance structures being electrically connected to a corresponding one of the first source/drain regions.