Selective memory scrubbing based on data type
A method for minimizing soft error rates within caches by controlling a memory scrubbing rate selectively for a cache memory at an individual bank level. More specifically, the disclosure relates to maintaining a predetermined sequence and process of storing all modified information of a cache in a subset of ways of the cache, based upon for example, a state of a modified indication within status information of a cache line. A cache controller includes a memory scrubbing controller which is programmed to scrub the subset of the ways with the modified information at a smaller interval (i.e., more frequently) compared to the rest of the ways with clean information (i.e., information where the information stored within the main memory is coherent with the information stored within the cache).
1. A cache system comprising:
a cache array, the cache array comprising a plurality of sections; and,
cache control logic, the cache control logic storing modified information to a subset of at least one of the plurality of sections; and,
a memory scrubbing controller, the memory scrubbing controller scrubbing the one of the plurality of sections at a first scrubbing rate and scrubbing another of the plurality of sections at a second scrubbing rate, the first scrubbing rate being faster than the second scrubbing rate; and wherein
if the one of the plurality of sections is full of modified information, then modified information is stored to a second of the plurality of sections and the first scrubbing rate is applied to the second of the plurality of sections.
2. The cache system of claim 1 wherein:
the memory scrubbing controller dynamically controls to which of the plurality of sections the first scrubbing rate signal is applied.
3. The cache system of claim 1 wherein:
the cache system uses a modified, exclusive, shared, invalid (MESI) protocol to maintain cache coherency.
4. The cache system of claim 3 wherein:
the modified information corresponds to a modified state within the MESI protocol.
5. The cache system of claim 1 wherein:
the cache control logic interacts with a cache replacement operation to determine when the one of a plurality of ways in a set contains modified data.
6. The cache system of claim 1 wherein:
the cache system is contained within a processor core.
7. The cache system of claim 1 wherein:
the second scrubbing rate is related to a speed of the processor core.
8. The cache system of claim 1 wherein:
the first scrubbing rate is five to twenty times faster than the second scrubbing rate.
9. The cache system of claim 1 wherein:
the first scrubbing rate is substantially every one million cycles and the second scrubbing rate is substantially every ten million cycles.
10. A method for improving error resilience comprising:
providing a cache array, the cache array comprising a plurality of sections; and,
storing modified information to a subset of at least one of the plurality of sections;
performing a scrubbing operation on the one of the plurality of sections at a first scrubbing rate; and,
performing a scrubbing operation on another of the plurality of sections at a second scrubbing rate, the first scrubbing rate being faster than the second scrubbing rate; and wherein
if the one of the plurality of sections is full of modified information, then modified information is stored to a second of the plurality of sections and the first scrubbing rate is applied to the second of the plurality of sections.
11. The method of claim 10 further comprising:
dynamically controlling to which of the plurality of sections the first scrubbing rate is applied.
12. The method of claim 10 wherein:
using a modified, exclusive, shared, invalid (MESI) protocol to maintain cache coherency.
13. The method of claim 12 wherein:
the modified information corresponds to a modified state within the MESI protocol.
14. The method of claim 10 further comprising:
applying a cache replacement operation to determine when one of a plurality of ways in a set contains modified data.
15. The method of claim 10 wherein:
the cache array is contained within a processor core.
16. The method of claim 14 wherein:
the second scrubbing rate is related to a speed of the processor core.
17. The method of claim 10 wherein:
the first scrubbing rate is five to twenty times faster than the second scrubbing rate.
18. The method of claim 10 wherein:
the first scrubbing rate is substantially every one million cycles and the second scrubbing rate is substantially every ten million cycles.