IP Library Granted Patent US 8,650,515
Granted Patent B2
US 8,650,515 · App. 13/588,975 · Granted Feb 11, 2014

Validation of circuit definitions

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Quick Facts
Patent No.
US 8,650,515
App. No.
13/588,975
Granted
Feb 11, 2014
Kind
B2
Abstract

Systems and methods for validating a circuit design are described. The circuit validation includes determining a subset of checks to apply to a portion of the overall circuit based on the pin type composition of the circuit portion.

Claims (78)

1. A method for use in validating a circuit design, the method implemented in a computer system comprising a processor and a memory storing instructions, which when executed by the processor configure the computer system to perform the method comprising:

accessing circuit information specifying a plurality of connections between a plurality of components of at least a portion of the circuit design;

retrieving from a plurality of parametric models a respective parametric model for each of the plurality of components specified in the received circuit information, each of the parametric models specifying a pin type, from a plurality of pin types, and operating parameters of each pin of the associated component;

determining a plurality of checks to apply to at least the portion of the circuit design based on the pin types of the plurality of components, each of the plurality of checks associated with characteristics of connected components to identify potential connection problems in the portion of a circuit definition;

applying the plurality of determined checks to at least the portion of the circuit definition, wherein one or more of the plurality parametric models comprises a plurality of operating parameters for a pin of the associated component, each associated with a selecting condition for selecting its use with the component; and

determining one of the operating parameters of the pin to use based on the selecting condition, wherein the selecting condition specifies an operating parameter of another pin of the associated component, and determining one of the operating parameters comprises determining the operating parameter of the other pin based on one or more connected components.

2. The method of claim 1 , wherein the plurality of pin types are a predefined set of pin types.

3. The method of claim 1 , wherein the circuit information comprises a netlist comprising a plurality of nets specifying the plurality of connections between a plurality of component references and a Bill Of Material (BOM) associating each of the plurality of component references with a respective component.

4. The method of claim 3 , wherein determining the plurality of checks to apply comprises determining checks to apply to each net of the netlist.

5. The method of claim 3 , wherein determining the plurality of checks to apply comprises:

determining extended nets for each net in the netlist; and

determining checks to apply to each of the determined extended nets.

6. The method of claim 5 , wherein determining checks to apply to each of the determined extended nets comprises:

determining a composition of pin types in the respective extended net; and

selecting a subset of checks from a plurality of checks based on the pin type composition of the extended net.

7. The method of claim 1 , wherein accessing the circuit information comprises receiving the circuit information from a circuit design tool.

8. The method of claim 7 , wherein the portion of the circuit design comprises a net in the circuit that was modified by the circuit design tool.

9. The method of claim 8 , further comprising displaying results of the applied checks in the circuit design tool.

10. The method of claim 1 , further comprising displaying results of the applied checks.

11. The method of claim 1 , wherein each of the parametric models specify one or more of:

a pin number;

a pin name;

the pin type;

a maximum input voltage;

a minimum input voltage;

an input voltage representing a logic level high;

an input voltage representing a logic level low;

a maximum output voltage;

a minimum output voltage;

an output voltage representing a logic level high;

an output voltage representing a logic level low;

a driver qualifier specifying a voltage for selecting one of a plurality of operating parameters for a pin;

a driver power rail specifying a pin associated with the driver qualifier;

a maximum supply voltage; and

a minimum supply voltage.

12. A system for validating a circuit design comprising:

a processor for executing instructions; and

a memory for storing instructions, the instructions when executed by the processor configuring the system to:

access circuit information specifying a plurality of connections between a plurality of components of at least a portion of the circuit design;

retrieve from a plurality of parametric models a respective parametric model for each of the plurality of components specified in the received circuit information, each of the parametric models specifying a pin type, from a plurality of pin types, and operating parameters of each pin of the associated component;

determine a plurality of checks to apply to at least the portion of the circuit design based on the pin types of the plurality of components, each of the plurality of checks associated with characteristics of connected components to identify potential connection problems in the portion of a circuit definition;

apply the plurality of determined checks to at least the portion of the circuit definition, wherein one or more of the plurality parametric models comprises a plurality of operating parameters for a pin of the associated component, each associated with a selecting condition for selecting its use with the component; and

determine one of the operating parameters of the pin to use based on the selecting condition, wherein the selecting condition specifies an operating parameter of another pin of the associated component, and determining one of the operating parameters comprises determining the operating parameter of the other pin based on one or more connected components.

13. The system of claim 12 , wherein the plurality of pin types are a predefined set of pin types.

14. The system of claim 12 , wherein the circuit information comprises a netlist comprising a plurality of nets specifying the plurality of connections between a plurality of component references and a Bill Of Material (BOM) associating each of the plurality of component references with a respective component.

15. The system of claim 14 , wherein configuring the system to determine the plurality of checks to apply comprises configuring the system to determine checks to apply to each net of the netlist.

16. The system of claim 14 , wherein configuring the system to determine the plurality of checks to apply comprises configuring the system to:

determine extended nets for each net in the netlist; and

determine checks to apply to each of the determined extended nets.

17. The system of claim 16 , wherein configuring the system to determine checks to apply to each of the determined extended nets comprises configuring the system to:

determine a composition of pin types in the respective extended net; and

select a subset of checks from a plurality of checks based on the pin type composition of the extended net.

18. The system of claim 12 , wherein configuring the system to access the circuit information comprises configuring the system to receive the circuit information from a circuit design tool.

19. The system of claim 18 , wherein the portion of the circuit design comprises a net in the circuit that was modified by the circuit design tool.

20. The system of claim 19 , wherein the instructions further configure the system to display results of the applied checks in the circuit design tool.

21. The system of claim 12 , wherein the instructions further configure the system to display results of the applied checks.

22. The system of claim 12 , wherein each of the parametric models specify one or more of:

a pin number;

a pin name;

the pin type;

a maximum input voltage;

a minimum input voltage;

an input voltage representing a logic level high;

an input voltage representing a logic level low;

a maximum output voltage;

a minimum output voltage;

an output voltage representing a logic level high;

an output voltage representing a logic level low;

a driver qualifier specifying a voltage for selecting one of a plurality of operating parameters for a pin;

a driver power rail specifying a pin associated with the driver qualifier;

a maximum supply voltage; and

a minimum supply voltage.

23. A non-transitory computer readable memory containing instructions for carrying out a method for use in validating a circuit design, the method comprising:

accessing circuit information specifying a plurality of connections between a plurality of components of at least a portion of the circuit design;

retrieving from a plurality of parametric models a respective parametric model for each of the plurality of components specified in the received circuit information, each of the parametric models specifying a pin type, from a plurality of pin types, and operating parameters of each pin of the associated component;

determining a plurality of checks to apply to at least the portion of the circuit design based on the pin types of the plurality of components, each of the plurality of checks associated with characteristics of connected components to identify potential connection problems in the portion of a circuit definition;

applying the plurality of determined checks to at least the portion of the circuit definition, wherein one or more of the plurality parametric models comprises a plurality of operating parameters for a pin of the associated component, each associated with a selecting condition for selecting its use with the component; and

determining one of the operating parameters of the pin to use based on the selecting condition, wherein the selecting condition specifies an operating parameter of another pin of the associated component, and determining one of the operating parameters comprises determining the operating parameter of the other pin based on one or more connected components.

Assignments (6)
MERGER AND CHANGE OF NAME Recorded Jun 9, 2021
From: MENTOR GRAPHICS CORPORATION; SIEMENS INDUSTRY SOFTWARE INC.
To: SIEMENS INDUSTRY SOFTWARE INC.
Reel/Frame 056526/0054 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2019
From: MENTOR GRAPHICS (CANADA) ULC
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 047991/0543 →
MERGER AND CHANGE OF NAME Recorded Jan 14, 2019
From: VALYDATE INC.; MENTOR GRAPHICS (CANADA) LIMITED; MENTOR GRAPHICS (CANADA) LIMITED
To: MENTOR GRAPHICS (CANADA) LIMITED
Reel/Frame 048070/0546 →
CHANGE OF NAME Recorded Jan 14, 2019
From: MENTOR GRAPHICS (CANADA) LIMITED
To: MENTOR GRAPHICS (CANADA) ULC
Reel/Frame 048070/0595 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2017
From: ALAM, MICHAEL; CAMPBELL, PETER; CIANFAGLIONE, MARK
To: VALYDATE INC.
Reel/Frame 041645/0161 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2012
From: ALAM, MICHAEL; CAMPBELL, PETER; CIANFAGLIONE, MARK
To: VALYDATE INC.
Reel/Frame 028820/0447 →