Random timeslot controller for enabling built-in self test module
View Patent ↗A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.
1. A method comprising:
executing a security sensitive operation at a security sensitive module of an integrated circuit die; and
receiving a random value from a random value generator for randomly enabling or disabling a BIST (built-in self test) module of the integrated circuit die concurrently with executing the security operation to change power consumption of the integrated circuit die, the BIST module configured in a test mode of operation to test a portion of the integrated circuit die.
2. The method of claim 1 , wherein the security sensitive module includes a first processor core implementing the security sensitive operation by executing secure code, and the portion of the integrated circuit die includes a second processor core of the integrated circuit die.
3. The method of claim 2 , wherein in response to randomly enabling the BIST module, the BIST module accesses a memory of the second processor core.
4. The method of claim 3 , wherein randomly enabling or disabling the BIST module is in response to executing the security sensitive operation.
5. The method of claim 3 , wherein the BIST module accessing the memory includes writing randomly generated data to the memory.
6. The method of claim 1 , wherein randomly enabling or disabling the BIST module includes generating a randomly enabled or disabled signal at a linear feedback shift register module and randomly enabling or disabling the BIST module based upon whether the signal is enabled or disabled.
7. The method of claim 1 , wherein randomly enabling or disabling the BIST module to change power consumption includes enabling the BIST operation in response to an enable signal being randomly asserted, wherein an expected ratio of an asserted portion of the enable signal to a negated portion (the A/N ratio) of the enable signal is defined.
8. The method of claim 7 , wherein the A/N ratio is user defined.
9. The method of claim 7 , wherein the expected A/N ratio is expected to be obtained by transitioning the enable signal between being asserted and being negated a plurality of times, wherein the asserted portions of the enable signal have random durations.
10. The method of claim 7 , wherein the defined A/N ratio is randomly selected, and changes at random times.
11. The method of claim 1 , wherein randomly enabling of the BIST operation is based upon an environmental condition of the integrated circuit die.
12. The method of claim 1 , wherein executing the BIST operation is in response to setting a control bit in response to executing the security sensitive operation.
13. A device comprising:
a security sensitive module of an integrated circuit die to execute a security sensitive operation;
a BIST (built-in self test) module to test at least a portion of the integrated circuit die; and
a random value generator coupled to the security sensitive module and to the BIST module to randomly enable or disable the BIST module in response to the security sensitive module executing the security sensitive operation.
14. The device of claim 13 , wherein executing the security sensitive module includes executing security sensitive code at a first processer core, and wherein at least a portion of the integrated circuit die includes a second processor core.
15. The device of claim 13 , wherein in response to the random value generator enabling the BIST module, the BIST module accesses a cache memory of the second processor core.
16. The device of claim 13 , wherein in response to the random value generator enabling the BIST module, the BIST module accesses a memory of the integrated circuit die.
17. The device of claim 13 , wherein in response to the random value generator enabling the BIST module, the BIST module writes random information to a memory of the integrated circuit die.