Programmable resistive memory unit with multiple cells to improve yield and reliability
A method and system for a programmable resistive memory to improve yield and reliability has a plurality of programmable resistive units. Each programmable resistive unit can have at least one programmable resistive cell. Each programmable resistive cell can have a programmable resistive element with a first end coupled to a first supply voltage line and a second end coupled to at least one diode serving as program selector. Each diode can have at least first and second terminals with first and second types of dopants, with the second terminal being coupled to a second supply voltage line. The first and second terminals of the diode can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure.
1. A programmable resistive memory, comprising:
a plurality of programmable resistive memory units, at least a plurality of the programmable resistive memory units having at least one programmable resistive memory cells;
each of the programmable resistive memory cells having a programmable resistive element and at least one diode, which serves as a program selector;
the programmable resistive element in each of the programmable resistive memory cells has a first end coupled to a first supply voltage line, a second end coupled to a first terminal of the diode, and the second terminal of the diode coupled to a second supply voltage line;
each of the programmable resistive memory cells being configured to program into a second logic state by applying a first voltage to the first supply voltage line and a second voltage to the second supply voltage line to turn on the diode serving as program selector; and
the programmable resistive memory units being configured to store a second logic state if at least one of the programmable resistive memory cells corresponding thereto has a second logic state.
2. A programmable resistive memory as recited in claim 1 , wherein the at least one diode has at least one first type of region having a first type of dopant and a second type of region having a second type of dopant, both the first type and the second type regions residing in a polysilicon structure.
3. A programmable resistive memory as recited in claim 1 , wherein the at least one diode has at least one first active region having a first type of dopant and a second active region having a second type of dopant, with both the first and second active regions being source/drain of MOS devices residing in the same MOS well.
4. A programmable resistive memory as recited in claim 1 , wherein the programmable resistive element is a One-Time Programmable (OTP) element.
5. A programmable resistive memory as recited in claim 4 , wherein the One-Time Programmable (OTP) element is an electrical fuse or electrical anti-fuse.
6. A programmable resistive memory as recited in claim 4 , wherein the One-Time Programmable (OTP) element is an electrical fuse fabricated from at least one portion of silicided polysilicon.
7. A programmable resistive memory as recited in claim 1 , wherein the programmable resistive element is a phase-change film.
8. A programmable resistive memory as recited in claim 1 , wherein the programmable resistive element is a Magnetic Tunnel Junction (MTJ).
9. A programmable resistive memory as recited in claim 1 , wherein the second supply voltage lines for a plurality of the programmable resistive cells are coupled together.
10. A One-Time Programmable (OTP) memory, comprising:
a plurality of One-Time Programmable (OTP) memory units, each of the OTP memory units having at least one One-Time Programmable (OTP) memory cell;
each of the OTP memory cells having a One-Time Programmable (OTP) element and at least one diode, which serves as a program selector,
wherein first and second terminals of the diode have first and second types of dopants respectively being built as the source/drain of MOS devices in a well for MOS devices or on the same polysilicon structure;
the OTP element in each of the OTP memory cells has a first end coupled to a first supply voltage line, a second end coupled to a first terminal of the diode, and a second terminal of the diode coupled to a second supply voltage line; and
each of the OTP memory cells being configured to program into a second logic state by applying a first voltage to the first supply voltage line and a second voltage to the second supply voltage line to turn on the diode as program selector.
11. A One-Time Programmable (OTP) memory as recited in claim 10 , wherein the OTP element is an electrical fuse or electrical anti-fuse.
12. A One-Time Programmable (OTP) memory as recited in claim 10 , wherein the OTP element is an interconnect constructed from a CMOS gate.
13. A One-Time Programmable (OTP) memory as recited in claim 10 , wherein the OTP element has at least a portion of silicided polysilicon.
14. An electronic system, comprising:
a processor; and
a programmable resistive memory operatively connected to the processor, the programmable resistive memory includes at least a plurality of programmable resistive units for providing data storage, each of the programmable resistive units having at least one programmable resistive memory cells;
each of the programmable resistive memory cells having a programmable resistive element and at least one diode, which serves as a program selector;
the programmable resistive element in each of the programmable resistive memory cells has a first end coupled to a first supply voltage line, a second end coupled to a first terminal of the diode, and the second terminal of the diode coupled to a second supply voltage line; and
each of the programmable resistive memory cell being configured to program into a second logic state by applying a first voltage to the first supply voltage line and a second voltage to the second supply voltage line to turn on the diode serving as program selector.
15. An electronic system as recited in claim 14 , wherein at least one diode has at least one first type of region having a first type of dopant and a second type of region having a second type of dopant, with both the first and second regions residing in a polysilicon structure.
16. An electronic system as recited in claim 14 , wherein the at least one diode has at least one first active region having a first type of dopant and a second active region having a second type of dopant, with both the first and second active regions being source/drain of MOS devices residing in the same MOS well.
17. An electronic system as recited in claim 14 , wherein the programmable resistive element is an interconnect constructed from a CMOS gate.
18. A method for providing a programmable resistive memory, comprising:
providing a plurality of programmable resistive units, at least one of the programmable resistive units including at least one programmable resistive cells, each of the programmable resistive cells including (i) a programmable resistive element having a first end coupled to a first supply voltage line and a second end coupled to a first terminal of at least one of the diodes, and (ii) the diode with the first and second terminals doped with a first and second types of dopants having a second terminal coupled to a second supply voltage line;
each of the programmable resistive memory cells being configured to program into a second logic state by applying a first voltage to the first supply voltage line and a second voltage to the second supply voltage line to turn on the diode serving as program selector; and
the programmable resistive memory units being configured to have a second logic state if at least one of the programmable resistive memory cells corresponding thereto have a second logic state.
19. A method as recited in claim 18 , wherein the at least one diode has at least one first type of region having a first type of dopant and a second type of region having a second type of dopant, with both of the first type and second type regions residing in a polysilicon structure.
20. A method as recited in claim 19 , wherein the at least one diode has at least one first active region having a first type of dopant and a second active region having a second type of dopant, with both the first and second active regions being source/drain of MOS devices residing in the same MOS well.