Granted Patent B2

US 9,159,702 · App. 13/591,924 · Granted Oct 13, 2015

Abstract

Claims (42)

1. A method for fabricating stacked microelectronic packages, comprising:

arranging a plurality of microelectronic device panels in a panel stack, each microelectronic device panel containing plurality of microelectronic devices and a plurality of package edge conductors extending therefrom;

creating trenches in the panel stack exposing the plurality of package edge conductors;

forming a plurality of sidewall conductors interconnecting different ones of the package edge conductors exposed through the trenches, forming comprising:

depositing an electrically-conductive material into the trenches contacting the plurality of package edge conductors to produce conductor-filled trenches; and

removing selected portions of the electrically-conductive material to produce a series of linearly-spaced vertical openings in each conductor-filled trench, the series of linearly-spaced vertical openings partially defining the plurality of sidewall conductors; and

separating the panel stack into a plurality of stacked microelectronic packages each comprising at least first and second sidewall conductors, the first sidewall conductor electrically isolated from the second sidewall conductor by one of the linearly-spaced vertical openings during removal of selected portions of the electrically-conductive material.

2. A method according to claim 1 wherein depositing comprises dispensing an electrically-conductive paste into the trenches.

3. A method according to claim 2 wherein dispensing comprises filling the trenches at least partially with a metal-containing epoxy.

4. A method according to claim 2 wherein the selected portions of the electrically-conductive material are removed by drilling the series of linearly-spaced vertical openings into the electrically-conductive paste after dispensing the electrically-conductive paste into the trenches.

5. A method according to claim 4 wherein drilling comprises removing vertical columns of the electrically-conductive paste utilizing a laser ablation process.

6. A method according to claim 1 wherein arranging comprises bonding together at least two neighboring microelectronic device panels to produce the panel stack.

7. A method according to claim 1 wherein the plurality of microelectronic device panels are produced using a process comprising:

embedding microelectronic devices in an encapsulant having a device surface through which the microelectronic devices are exposed; and

forming the package edge conductors over the device surface and electrically coupled to the microelectronic devices.

8. A method according to claim 1 wherein the microelectronic device panels comprise dicing streets to which the plurality of package edge conductors extend, and wherein the step of arranging comprises arranging the device panels in a panel stack such that the dicing streets of the device panels at least partially overlap, as taken along a centerline of the panel stack.

9. A method according to claim 1 wherein the microelectronic device panels comprise dicing streets to which the plurality of package edge conductors extend, and wherein the step of creating comprises cutting trenches into the panel stack along the dicing streets and transecting the plurality of package edge conductors.

10. A method according to claim 9 wherein cutting comprises cutting trenches into the panel stack and having a first predetermined width, and wherein separating comprises singulating the panel stack into a plurality of stacked microelectronic packages utilizing a saw having a blade thickness less than the first predetermined width.

11. A method according to claim 1 wherein creating comprises cutting trenches in the panel stack such that a portion of each of the plurality of package edge conductors is removed.

12. A method according to claim 1 further comprising depositing a dielectric material between the sidewall conductors.

13. A method for fabricating stacked microelectronic packages, comprising:

stacking at least first and second device panels to produce a panel stack, the first microelectronic device panel comprising:

a molded panel body;

a plurality of microelectronic devices embedded in the molded panel body;

dicing streets bordering the plurality of microelectronic devices; and

a plurality of package edge conductors extending from the microelectronic devices to the dicing streets;

cutting trenches into the panel stack along the dicing streets exposing the plurality of package edge conductors and at least partially defining one or more sidewalls of each of the plurality of stacked microelectronic packages;

filling the trenches with an electrically-conductive material to produce electrically-conductive bodies within the trenches contacting the package edge conductors exposed through the trench sidewalls;

forming a plurality of spaced-apart vertical openings in each electrically-conductive bodies to at least partially define a plurality of sidewall conductors electrically-coupled to the plurality of package edge conductors, the plurality of spaced-apart vertical openings extending into the sidewalls of the plurality of stacked microelectronic packages to provide electrical isolation between the neighboring sidewall conductors of each stacked microelectronic package; and

after forming the plurality of spaced-apart vertical openings, singulating the panel stack into the plurality of stacked microelectronic packages to fully define the sidewall conductors and to separate the plurality of stacked microelectronic packages.

14. A method according to claim 13 further comprising producing a contact formation over a first stacked microelectronic package included within the plurality of stacked microelectronic packages prior to or after singulating the panel stack, at least one of the plurality of sidewall conductors electrically coupling at least one microelectronic device included within the first stacked microelectronic package to a contact included within the contact formation.

15. A method according to claim 13 wherein filling comprises dispensing an electrically-conductive paste into the trenches to produce a plurality of filled trenches, and wherein forming comprises drilling openings into the filled trenches each spaced-apart vertical opening extending across and through a filled trench.

16. A method according to claim 13 wherein cutting comprises cutting trenches into the panel stack extending through the second microelectronic device panel and extending into, but not through the first microelectronic device panel.

17. A method for fabricating stacked microelectronic packages, comprising:

forming a trench between first and second stacked microelectronic packages extending along a first axis, the first and second stacked microelectronic packages each including a plurality of package edge conductors extending to the trench and a sidewall defined, at least in part, by the trench;

filling the trench with an electrically-conductive material to produce a conductor-filled trench;

forming linearly-spaced vertical openings in the conductor-filled trench to at least partially define a plurality of sidewall conductors electrically-coupled to the plurality of package edge conductors, the linearly-spaced vertical openings spaced along the first axis and extending into the sidewalls of the first and second stacked microelectronic packages; and

singulating the first and second microelectronic stacked microelectronic packages to fully define the plurality of sidewall conductors and to separate the first and second microelectronic stacked microelectronic packages;

wherein at least two first neighboring sidewall conductors included within the first microelectronic package are electrically isolated from one another by removal of material from the conductor-filled trench during formation of the linearly-spaced vertical openings, and wherein at least two second neighboring the sidewall conductors included within the second microelectronic package are electrically isolated from one another by removal of material from the conductor-filled trench during formation of the linearly-spaced vertical openings.

18. A method according to claim 17 wherein the linearly-spaced vertical openings extend at least partially through the conductor-filled trench, as taken along a second axis perpendicular to the first axis, and across the conductor-filled trench, as taken along a third axis orthogonal to the first and second axes.

19. A method according to claim 17 wherein the linearly-spaced vertical openings are interleaved with the plurality of sidewall conductors, as taken along the first axis.

20. A method according to claim 17 wherein forming comprises cutting the trench between the first and second stacked microelectronic package utilizing a first saw blade having a first thickness, wherein filling comprises filling the trench with a metal-containing epoxy to produce the conductor filled trench, wherein forming comprises removing vertical columns of material from the conductor-filled trench utilizing a laser ablation process to produce the linearly-spaced vertical openings through the trench partially defining the plurality of sidewall conductors, and wherein singulating comprises separating the first and second microelectronic packages by cutting through the partially defined sidewall conductors utilizing a second saw blade having a second thickness less than the first thickness.

Assignments (31)