IP Library Granted Patent US 8,729,607
Granted Patent B2
US 8,729,607 · App. 13/595,022 · Granted May 20, 2014

Needle-shaped profile finFET device

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Quick Facts
Patent No.
US 8,729,607
App. No.
13/595,022
Granted
May 20, 2014
Kind
B2
Abstract

Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel.

Claims (42)

1. A semiconductor device comprising:

a fin field effect transistor (finFET) structure, the finFET structure comprising:

a silicon substrate;

a first fin formed on the silicon substrate, wherein the first fin has a needle-shaped profile;

wherein the first fin has a first part under a gate, and a second part, which is continuous with the first part; the second part having a cross-sectional shape different from the first part, and wherein the second part has the needle-shaped profile, and

a portion of the first part, which is at an interface with the second part, and is exposed resulting from a difference between the first part and the second part in cross-sectional shape, is covered with the doped layer at a vicinity of a top of the needle-shaped profile of the first fin;

a second fin formed on the silicon substrate, wherein the first fin and second fin are formed on the same side of the silicon substrate with a trough located between the first fin and the second fin;

a buffer layer formed epitaxially on the first fin, the second fin and the trough located between the first fin and the second fin; and

a doped layer formed epitaxially on the buffer layer,

wherein the doped layer covers the first fin and the second fin, and an upper surface of the doped layer has a substantially flat profile.

2. The semiconductor device of claim 1 , wherein the needle-shaped profile of the first fin has a profile of an isosceles triangle.

3. The semiconductor device of claim 1 , wherein the needle-shaped profile of the first fin comprises a first side and a second side, where a first edge of the first side and a first edge of the second side form a point of the needle-shaped profile, and a second edge of the first side and a second edge of the second side intersect the silicon substrate to form a triangular structure.

4. The semiconductor device of claim 1 , wherein the buffer layer comprises at least one of a carbon silicon (Si:C) layer or a carbon-doped silicon germanium (SiGe:C) layer.

5. The semiconductor device of claim 1 , wherein the buffer layer comprises a SiH4-based SiGe layer or a SiH4-based SiGeC layer.

6. The semiconductor device of claim 1 , wherein the doped layer comprising phosphorus-doped silicon (Si:P).

7. The semiconductor device of claim 1 , wherein the doped layer comprising a silicon-germanium-boron (SiGeB) compound or a silicon-germanium-boron-carbon (SiGeBC) compound.

8. The semiconductor device of claim 1 , wherein the silicon substrate, the first fin, and the second fin comprises silicon aligned on a first plane disparate to a second plane utilized to epitaxially grow at least one of the buffer layer or the doped layer.

9. The semiconductor device of claim 8 , wherein the first plane and second plane are selected such that formation of at least one of the buffer layer or the doped layer generates a stress in at least one of the substrate, first fin, or second fin.

10. The semiconductor device of claim 1 , wherein substantially no buffer layer is formed on a top of the needle-shaped profile of the first fin and a needle-shaped profile of the second fin.

11. A semiconductor device comprising:

a fin field effect transistor (finFET) structure, the finFET structure comprising:

a silicon substrate;

a first fin formed on the silicon substrate, wherein the first fin has a needle-shaped profile, wherein the needle-shaped profile of the first fin has a profile of an isosceles triangle;

a second fin formed on the silicon substrate, wherein the second fin has a needle-shaped profile, wherein the needle-shaped profile of the second fin has a profile of an isosceles triangle, the first fin and second fin are formed on the same side of the silicon substrate with a trough located between the first fin and the second fin; and

a buffer layer formed epitaxially on the first fin: and the second fin and the trough located between the first fin and the second fin; and

a doped layer formed epitaxially on the buffer layer, wherein

each of the first fin and the second fin has a first part under a gate, and a second part, which is continuous with the first part; the second part having a cross-sectional shape different from the first part, and wherein the second part has the needle-shaped profile, and

a portion of the first part, which is at an interface with the second part, and is exposed resulting from a difference between the first part and the second part in cross-sectional shape, is covered with the doped layer at a vicinity of a top of the needle-shaped profile of the first fin and the second fin.

12. The semiconductor device of claim 11 , wherein the silicon substrate, the first fin, and the second fin comprise silicon aligned on a first plane and growth of the buffer layer generates stress in at least one of the substrate, the first fin, or the second fin in a direction disparate to the first plane.

13. The semiconductor device of claim 11 , wherein the first part of the first fin has the cross-sectional shape of a rectangular.

14. The semiconductor device of claim 11 , wherein the doped layer covers the first fin and the second fin, and an upper surface of the doped layer has a substantially flat profile.

15. The semiconductor device of claim 14 , wherein substantially no buffer layer is formed on the top of the needle-shaped profile of the first fin.

16. A method for forming a fin field effect transistor (finFET) semiconductor device comprising:

forming a silicon substrate;

forming a first fin and a second fin on the surface of the silicon substrate; wherein the first fin and second fin are formed on the same side of the silicon substrate with a trough located between the first fin and the second fin, and each of the first fin and the second fin has a needle-shaped profile, and

wherein the first fin has a first part under a gate, and a second part, which is continuous with the first part; the second part having a cross-sectional shape different from the first part, and wherein the second part has the needle-shaped profile, and

a portion of the first part, which is at an interface with the second part, and is exposed resulting from a difference between the first part and the second part in cross-sectional shape, is covered with the doped layer at a vicinity of a top of the needle-shaped profile of the first fin;

forming, epitaxially, a buffer layer on the first fin, the second fin and the trough located between the first fin and the second fin; and

forming, epitaxially, a doped layer on the buffer layer,

wherein the doped layer covers the first fin and the second fin, and an upper surface of the doped layer has a substantially flat profile.

17. The method of claim 16 , wherein the silicon substrate, the first fin, and the second fin comprise silicon aligned on a first plane disparate to a second plane utilized to epitaxially grow at least one of the buffer layer or the doped layer, wherein the first plane and second plane are selected such that during forming of at least one of the buffer layer of the doped layer facilitates generating a stress in at least one of the substrate, the first fin, or the second fin.

18. The semiconductor device of claim 16 , wherein substantially no buffer layer is formed on a top of the needle-shaped profile of the first fin and the second fin.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 11, 2017
From: TOSHIBA CORPORATION
To: MICROSOFT TECHNOLOGY LICENSING, LLC
Reel/Frame 041333/0955 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2013
From: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 031109/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2012
From: ITOKAWA, HIROSHI; HOKAZONO, AKIRA
To: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
Reel/Frame 028850/0413 →