IP Library Granted Patent US 8,683,177
Granted Patent B2
US 8,683,177 · App. 13/596,495 · Granted Mar 25, 2014

Content addressable memory (CAM) device and method for updating data

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,683,177
App. No.
13/596,495
Granted
Mar 25, 2014
Kind
B2
Abstract

A content addressable memory (CAM) ( 100 ) can include a CAM memory array ( 102 ) having both a data field ( 102 - 0 ) and a mask field ( 102 - 1 ). A multiplexer (MUX) ( 108 ) can selectively load data from either a register ( 104 ) or an external data input ( 106 ) to one or both fields ( 102 - 0 and 102 - 1 ) of CAM memory array ( 102 ).

Claims (37)

1. A content addressable memory (CAM), comprising:

a CAM memory array including a first field configured to store data and a second field configured to store mask data corresponding to the data in the first field;

a register coupled to a data input and configured to receive the data from the data input; and

a circuit coupled to the register, to the data input, and to the first and second fields of the CAM memory array, and configured to selectively provide the data from the register to the first field or provide the mask data from the data input to the second field of the CAM memory array.

2. The CAM of claim 1 , wherein the circuit comprises: a MUX configured to load the data from the register to the first field of the CAM memory array, and to load the mask data from the data input to the second field of the CAM memory array.

3. The CAM of claim 1 , wherein the register is configured to store search key data from a search operation.

4. The CAM of claim 1 , wherein the circuit comprises: a control input configured to receive learn instruction data.

5. The CAM of claim 4 , wherein the learn instruction data comprises: a bit in a learn instruction applied to the CAM.

6. The CAM of claim 1 , wherein the circuit is configured to load the data into the first field of the CAM memory array and to load the mask data into the second field of the CAM memory array.

7. The CAM of claim 1 , further comprising:

N data inputs, where N is a whole number greater than 2; and

wherein the circuit is configured to load the mask data from one of the N data inputs to the second field of the CAM memory array.

8. The CAM of claim 1 , further comprising:

M registers, where M is a whole number greater than 1; and

wherein the circuit is configured to load the data from one of the M registers to the first field of the CAM memory array.

9. A method to store data in a content addressable memory (CAM), comprising:

storing data from a first data input in a register of the CAM;

receiving mask data corresponding to the data from a second data input; and

selecting to load, using a circuit, the data or the mask data from the register or the second data input to first or second fields of the CAM.

10. The method of claim 9 , wherein the selecting step comprises using the circuit to provide first data from the register to the first field of the CAM and the mask data from the second data input to the second field of the CAM.

11. The method of claim 9 , wherein the selecting step comprises loading the mask data into the second field and then loading the data into the first field.

12. The method of claim 9 , further comprising:

executing a search operation; and

loading a search key of the search operation into the register as the data.

13. The method of claim 9 , further comprising:

executing a learn operation in response to a learn instruction; and

wherein the selecting step comprises selecting the data or the mask data according to at least one bit of the learn instruction.

14. A content addressable memory (CAM) device, comprising:

a CAM array having a data field with a plurality of entries and a mask field that stores mask values corresponding to the plurality of entries; and

a selection circuit comprising a first input configured to receive a first data value, a second input coupled to a register, and an output coupled to the CAM array,

wherein the register stores a search key value following a search operation.

15. The CAM device of claim 14 , wherein the selection circuit comprises: a control input configured to receive learn instruction data.

16. The CAM device of claim 15 , wherein the selection circuit further comprises: a control input coupled to a signal that corresponds to a bit value of the learn instruction.

17. The CAM device of claim 14 , wherein the selection circuit is configured to couple a search key value from a previous search operation to the data field, and a corresponding mask value from an external input to the mask field in response to a learn operation command.

18. The CAM device of claim 14 , wherein the selection circuit is coupled to the second input so as to receive a second data value from one of a plurality of data inputs.

19. The CAM device of claim 14 , wherein the first input of the selection circuit is coupled to a plurality of registers.

20. The CAM device of claim 14 , wherein the first data value is an externally applied data value.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2012
From: CYPRESS SEMICONDUCTOR CORPORATION
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 028861/0081 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2012
From: SMITH, SCOTT
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 028860/0943 →