Diode segmentation in memory
View Patent ↗Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.
1. A memory device, comprising:
a group of memory cells, each cell connected in series between a local first access line and a respective one of a plurality of second access lines;
a segmentation element connected between the local first access line and a global first access line;
a first biasing line;
a second biasing line;
a first biasing device connected between the first biasing line and the local first access line; and
a second biasing device connected between the second biasing line and the local first access line;
wherein the first and second biasing lines are configured to receive a same voltage during an access operation.
2. The memory device of claim 1 , wherein the first biasing device is configured to conduct current in a direction opposite to the direction in which the second biasing device is configured to conduct current.
3. The memory device of claim 1 , wherein the biasing devices are diodes.
4. The memory device of claim 1 , wherein the segmentation element is a diode.
5. The memory device of claim 1 , wherein the segmentation element comprises a pair of diodes connected in parallel between the local first access line and the global first access line.
6. The memory device of claim 3 , wherein the diodes are uni-directional.
7. The memory device of claim 3 , wherein the diodes are bi-directional.
8. The memory device of claim 1 , wherein the segmentation element comprises a first segmentation element and wherein the plurality of second access lines comprise a plurality of local second access lines, and further comprising a plurality of global second access and a plurality of second segmentation elements, wherein each of the plurality of second segmentation elements is connected between a respective one of the local second access lines and a respective one of the global second access lines.
9. A memory device, comprising:
a group of memory cells, each cell connected in series between a local first access line and a respective one of a plurality of second access lines;
a segmentation diode connected between the local first access line and a global first access line;
a first biasing diode connected between a first biasing line and the local first access line; and
a second biasing diode connected between a second biasing line and the local first access line;
wherein the first and second biasing lines are configured to receive a same voltage during an access operation.
10. The memory device of claim 9 , wherein the first biasing diode is configured to conduct current in a direction opposite to the direction in which the second biasing diode is configured to conduct current.
11. A memory device, comprising:
a group of memory cells, each cell connected in series between a local first access line and a respective one of a plurality of second access lines; and
a segmentation diode connected between the local first access line and a global first access line;
wherein the segmentation diode comprises a first segmentation diode and further comprising a second segmentation diode connected in parallel with the first segmentation diode between the local first access line and the global first access line.
12. The memory device of claim 10 , wherein the segmentation diode is uni-directional.
13. The memory device of claim 10 , wherein the segmentation diode is bi-directional.
14. A memory array, comprising:
a block of variable resistance memory cells connected to a global access line by a segmentation element, and connected to a first biasing line by a first biasing device and to a second biasing line by a second biasing device;
wherein the first and second biasing lines are configured to receive a same voltage during an access operation.
15. The memory array of claim 14 , wherein the block further comprises:
a plurality of variable resistance memory cells at intersections of local access lines, each memory cell comprising a programmable element and a select device connected in series between its respective local access lines.
16. The memory array of claim 14 , wherein the segmentation element is a diode.
17. The memory array of claim 14 , wherein the biasing devices are diodes.
18. The memory array of claim 14 , wherein the segmentation elements and the biasing devices are diodes.
19. A memory device, comprising:
a group of variable resistance memory cells connected to a local access line, wherein the local access line is connected to a global access line by a segmentation element;
a first biasing line;
a second biasing line;
a first biasing device connected between the first biasing line and the local access line; and
a second biasing device connected between the second biasing line and the local access line;
wherein the first and second biasing lines are configured to receive a same voltage during an access operation.
20. A method of operating a memory, comprising:
biasing a two terminal segmentation element for selected cells of a selected block of the memory to turn the segmentation element on;
biasing a two terminal segmentation element for unselected cells of a selected block of the memory to turn the segmentation element off; and
biasing segmentation elements for unselected blocks of the memory to turn the segmentation elements off.
21. The method of claim 20 , and further comprising:
biasing lines to reverse bias select devices of unselected cells of the memory.
22. The method of claim 20 , wherein biasing the two terminal segmentation element for cells of the memory comprises biasing a diode connected between a global access line of the memory and a local access line of the memory.
23. The method of claim 20 , wherein biasing segmentation elements for unselected blocks of the memory comprises biasing a plurality of diodes, each diode connected between a biasing line and a respective local access line.