Delay compensation for sigma delta modulator
View Patent ↗A continuous time delta-sigma modulator is provided that includes an integrator stage including a plurality of integrators; a quantizer to receive an input signal from the integrator stage and output a quantizer signal; a global feedback path providing feedback from the quantizer to the integrator stage; a local feedback path connecting the quantizer and a preceding integrator of the integrator stage configured to compensate for delay attributed to the global feedback path; and a delay compensation circuit. The delay compensation circuit is configured to calculate a delay value based on sources of additional delay within a local feedback loop, and to supply the additional delay value to the quantizer to compensate for delay within the local feedback loop.
1. A method for delay compensation implemented in a continuous time delta-sigma modulator having a global feedback loop and a local feedback loop, the method comprising:
identifying sources of delay within the local feedback loop, the local feedback loop compensating for delay attributed to the global feedback loop that provides for the stability and frequency shaping control of an output signal;
calculating an additional delay element based on the identified sources of delay within the local feedback loop; and
supplying the additional delay element to a quantizer to compensate for the sources of delay within the local feedback loop, the sources of delay including at least two of dither delay, quantizer delay and input delay.
2. The method according to claim 1 , wherein the input delay is integrator delay of the integrator connected to the quantizer via a local feedback path.
3. The method according to claim 2 , wherein the quantizer includes a preamplifier and a comparator, and the quantizer delay is delay associated with the preamplifier.
4. The method according to claim 2 , wherein the quantizer includes a sample and hold circuit and the quantizer delay is delay associated with the sample/hold setup time of the sample and hold circuit.
5. The method according to claim 1 , wherein the additional delay is a sum of the identified sources of delay within the local feedback loop.
6. The method according to claim 1 , wherein the local feedback path includes a digital to analog converter and a delay with a length is a time between two clock edges.
7. The method according to claim 1 , wherein the additional delay element is supplied to the quantizer to control timing between a quantizer clock and other clocks of the delta-sigma modulator.
8. A continuous time delta-sigma modulator comprising:
an integrator stage including a plurality of integrators;
a quantizer configured to receive an input signal from the integrator stage and output a quantizer signal;
a global feedback path providing feedback from the quantizer to the integrator stage;
a local feedback path connecting the quantizer and a preceding integrator of the integrator stage configured to compensate for delay attributed to the global feedback path; and
a delay compensation circuit configured to calculate a delay value based on sources of additional delay within a local feedback loop that includes the local feedback path, and to supply the additional delay value to the quantizer to compensate for at least two of dither delay, quantizer delay and input delay within the local feedback loop.
9. The continuous time delta-sigma modulator according to claim 8 , wherein the delay compensation circuit includes at least one of a plurality of inverters and a replica circuit of a component of the local feedback loop.
10. The continuous time delta-sigma modulator according to claim 9 , wherein the delay compensation circuit is configured to provide multiple delay values that are trimmable to compensate for the at least two of the dither delay, the quantizer delay and the input delay within the local feedback loop.
11. The continuous time delta-sigma modulator according to claim 8 , wherein the local feedback loop includes the local feedback path, an integrator of the integrator stage providing the input signal to the quantizer, and the quantizer.
12. The continuous time delta-sigma modulator according to claim 11 , wherein the calculated delay value is associated with the input delay attributed to the integrator of the integrator stage providing the input signal.
13. The continuous time delta-sigma modulator according to claim 11 , wherein the quantizer includes a preamplifier and a comparator and the quantizer delay is delay associated with the preamplifier.
14. The continuous time delta-sigma modulator according to claim 11 , wherein the quantizer includes a sample and hold circuit and the quantizer delay is delay associated with the sample/hold setup time of the sample and hold circuit.
15. The continuous time delta-sigma modulator according to claim 11 , wherein the calculated delay value is supplied to the quantizer to control timing between a quantizer clock and other clocks of the delta-sigma modulator.