Semiconductor device and method of manufacturing the same
A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities.
1. A semiconductor device, comprising:
word lines and interlayer insulating layers alternately stacked;
a channel layer penetrating the word lines and the interlayer insulating layers;
a tunnel insulating layer surrounding the channel layer; and
first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities, wherein the first charge trap layers are separated from each other.
2. The semiconductor device of claim 1 , wherein the first charge trap layers comprise nano-dots.
3. The semiconductor device of claim 1 , further comprising third charge trap layers interposed between the respective word lines and the interlayer insulating layers and interposed between the word lines and the first charge trap layers, respectively.
4. The semiconductor device of claim 1 , further comprising charge blocking layers surrounding the first charge trap layers, respectively, and interposed between the respective word lines and the interlayer insulating layer and between the word lines and the first charge trap layers, respectively.
5. The semiconductor device of claim 1 , further comprising charge blocking layers surrounding the first charge trap layers, respectively, and interposed between the first charge trap layers and the word lines, respectively.
6. The semiconductor device of claim 1 , wherein the first impurities comprise at least one of an N type impurities, a P type impurities, carbon (C), germanium (Ge), tin (Sn), and lead (Pb) or a combination thereof.
7. The semiconductor device of claim 1 , wherein a shallow trap level is formed in each of the first charge trap layers.
8. A semiconductor device, comprising:
word lines and interlayer insulating layers alternately stacked;
a channel layer penetrating the word lines and the interlayer insulating layers;
a tunnel insulating layer surrounding the channel layer;
first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities; and
second charge trap layers surrounding the tunnel insulating layer and interposed between the interlayer insulating layers and the tunnel insulating layer, respectively.
9. The semiconductor device of claim 8 , wherein the second charge trap layers are doped with second impurities having a different type from the first impurities.
10. A semiconductor device, comprising:
word lines and interlayer insulating layers alternately stacked;
a channel layer penetrating the word lines and the interlayer insulating layers;
a tunnel insulating layer surrounding the channel layer;
first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities;
first charge blocking layers interposed between the respective interlayer insulating layers and the tunnel insulating layer; and
second charge blocking layers surrounding the first charge trap layers, respectively, and interposed between the first charge trap layers and the word lines, respectively.