Fin-FET with mechanical stress of the fin perpendicular to the substrate direction
View Patent ↗A semiconductor device in one embodiment includes a semiconductor substrate, a fin disposed on a surface of the semiconductor substrate, an insulator including a gate insulator disposed on a side surface of the fin, and a gate electrode disposed on the insulator that is disposed on side surfaces of the fin and an upper surface of the fin. The device further includes a plurality of epitaxial stripe shaped layers disposed horizontally on the side surface of the fin at different heights, and an interlayer dielectric disposed on the semiconductor substrate to cover the fin and applying a stress to the fin and the epitaxial layers. Any two adjacent epitaxial layers along the fin height direction determine a gap and the gaps between adjacent layers increase or decrease with increasing distance from the substrate.
1. A semiconductor device comprising:
a semiconductor substrate;
a fin disposed on a surface of the semiconductor substrate;
an insulator including a gate insulator, said gate insulator disposed on side surfaces of the fin;
a gate electrode disposed on the insulator that is disposed on the side surfaces of the fin and also disposed on an upper surface of the fin;
a plurality of epitaxial stripe shaped layers disposed horizontally on the side surface of the fin at different heights; and
an interlayer dielectric disposed on the semiconductor substrate to cover the fin, and applying a stress to the fin and the epitaxial layers,
wherein along the fin height direction any two adjacent epitaxial layers determine a gap and the gaps between adjacent layers increase or decrease with increasing distance from the substrate.
2. The device of claim 1 , wherein the lowermost epitaxial layer and the bottom surface of the interlayer dielectric determine an additional gap and said gaps including said additional gap increase or decrease with increasing distance from the substrate.
3. The device of claim 1 , wherein the side surface of the fin is a (110) plane.
4. The device of claim 1 , wherein a fin extension direction of the fin is a <110> direction.
5. The device of claim 1 , wherein the interlayer dielectric applies a compressive stress or a tensile stress to the fin in the fin height direction.
6. The device of claim 1 , further comprising a punch through stopper diffusion layer disposed in the fin at a height lower than a height of the lowermost epitaxial layer.
7. A semiconductor device comprising:
a semiconductor substrate;
a fin disposed on a surface of the semiconductor substrate, and alternately including one or more first layers formed of first material and one or more second layers formed of second material different from the first material;
an insulator including a gate insulator, said gate insulator disposed on side surfaces of the fin;
a gate electrode disposed on on the insulator that is disposed on the side surfaces of the fin and also disposed on an upper surface of the fin;
a plurality of epitaxial stripe shaped layers disposed horizontally on side surfaces of respective second layers; and
an interlayer dielectric disposed on the semiconductor substrate to cover the fin, and applying a stress to the fin and the epitaxial layers,
wherein along the fin height direction any two adjacent epitaxial layers determine a gag and the gags between adjacent layers increase or decrease with increasing distance from the substrate.
8. The device of claim 7 , wherein lowermost epitaxial layer and the bottom surface of the interlayer dielectric determine an additional gap and said gaps including said additional gap increase or decrease with increasing distance from the substrate.
9. The device of claim 7 , wherein the side surface of the fin is a (110) plane.
10. The device of claim 7 , wherein a fin extension direction of the fin is a <110> direction.
11. The device of claim 7 , wherein the first material is first Semiconductor material, and the second material is second semiconductor material different from the first semiconductor material.
12. The device of claim 11 , further comprising a plurality of epitaxial layers disposed on side surfaces of respective first layers.
13. The device of claim 11 , wherein side surfaces of the first layers are recessed with respect to the side surfaces of the second layers in the fin.
14. The device of claim 13 , wherein insulators are embedded in regions where the side surfaces of the first layers are recessed in the fin.
15. The device of claim 7 , wherein the first material is insulating material, and the second material is semiconductor material.
16. The device of claim 7 , wherein
the first and second layers have side surfaces perpendicular to a fin extension direction of the fin, the side surfaces of the first layers being recessed with respect to the side surfaces of the second layers,
the interlayer dielectric is buried in regions where the side surfaces of the first layers are recessed in the fin, and
recessed amounts of the side surfaces of the first layers change in accordance with heights at which the first layers are located.