Memory devices, circuits and, methods that apply different electrical conditions in access operations

1. A memory device, comprising:

a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and

bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein

the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.

2. The memory device of claim 1 , wherein:

the memory elements comprise a programmable resistance material formed between two electrodes.

3. The memory device of claim 2 , wherein:

the memory elements each comprise a solid state electrolyte in which conductive regions can be formed and dissolved.

4. The memory device of claim 1 , further including:

a wear circuit configured to generate a heal indication for a physical block in response to predetermined wear conditions; and

the bias circuits apply the healing electrical conditions to the physical block in response to at least the heal indication.

5. The memory device of claim 4 , wherein:

the wear circuit is coupled to receive write request data, and includes a wear level store circuit to store wear level data for each physical block; wherein

the heal indication is generated in response to the wear level data for the physical blocks.

6. The memory device of claim 4 , wherein:

the wear circuit includes a characterization circuit that applies characterization conditions to at least one element of the physical block to generate state data; and

the heal indication is generated in response to the state data.

7. The memory device of claim 1 , wherein:

each physical block comprises a plurality of memory cells, each cell include

an access device coupled to a bit line common to a column of memory cells, and a word line common to a row of memory cells, and

at least one of the memory elements.

8. A system, comprising:

a plurality of memory blocks, each including a plurality of memory cells having at least one element programmable between impedance states, the memory blocks including active blocks and at least one spare block;

an address translation circuit configured to substitute accesses to one memory block for accesses to another memory block; and

a bias circuit configured to applying healing electrical conditions to the spare block; wherein

the healing electrical conditions are different from write conditions that write data to the memory cells and different from read conditions that read data from the memory cells, and reverse wear conditions of memory elements in the spare block.

9. The system of claim 8 , wherein:

the memory elements are two terminal elements programmable to form and dissolve a conductive path though at least one memory layer.

10. The system of claim 8 , wherein:

the memory blocks and address translation circuit are formed in a same integrated circuit (IC), and the address translation circuit translates address values received from a source external to the IC into physical addresses that access the memory blocks.

11. The system of claim 8 , wherein:

the memory blocks are formed in one integrated circuit (IC); and

the address translation circuit is formed in another IC.

12. The system of claim 8 , wherein:

a control circuit configured to transfer data from one memory block to the spare block and designate the one memory block as the new spare block.

13. The system of claim 8 , further including:

the memory blocks and bias circuit are formed in a same integrated circuit (IC);

a control circuit formed in the IC configured to generate heal control signals; and

the bias circuit is configured to apply the healing electrical conditions in response to the heal control signals.

14. The system of claim 8 , wherein:

the memory blocks and bias circuit are formed in a same integrated circuit (IC); and

the bias circuit is configured to apply the healing electrical conditions in response to commands received by the IC.

15. A method, comprising:

determining a wear status of each of a plurality of blocks, each block including a plurality of memory cells having at least one element programmable between impedance states;

if a block is determined to be worn, transferring data from the one block to a spare block; and

applying healing electrical conditions to the one block that reverse degradation of the memory elements of the worn block.

16. The method of claim 15 , wherein:

determining the wear status includes storing a wear value for each block that corresponding to the number of times the block has been subject to at least one type of access operation.

17. The method of claim 15 , wherein:

the healing electrical conditions are different from write conditions that write data into the cells.

18. The method of claim 15 , further including:

designating the one block as a new spare block for receiving data from a next block determined to be worn.

19. The method of claim 15 , further including:

after transferring data from the one block to the spare block, accessing the spare block with logical addresses previously used to access the one block.

20. The method of claim 15 , wherein:

translating received logical addresses into physical addresses to access less than all of the blocks.