Semiconductor light-emitting device

1. A semiconductor light-emitting device comprising:

a first conductivity type first semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in a (0001) surface;

a second conductivity type second semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in the (0001) surface;

a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, containing a nitride semiconductor crystal, and having an average lattice constant larger than a lattice constant of the first semiconductor layer; and

a first stress application layer provided on a side opposite to the light emitting layer of the first semiconductor layer and applying a compressive stress to the first semiconductor layer.

2. The device according to claim 1 , further comprising:

a second stress application layer provided on a surface on a side opposite to the light emitting layer of the second semiconductor layer and applying a compressive stress to the second semiconductor layer.

3. The device according to claim 2 , wherein

the second stress application layer contains Al x2 Ga 1-x2 N (0<x2<1).

4. The device according to claim 1 , wherein the first stress application layer contains Al x1 Ga 1-x1 N (0<x1≦1).

5. The device according to claim 1 , wherein

the first semiconductor layer contains a nitride semiconductor layer not containing impurities.

6. The device according to claim 1 , wherein

the light emitting layer includes a plurality of barrier layers and a well layer provided between the plurality of barrier layers; and

the average lattice constant is a lattice constant obtained by weighting the lattice constant of the barrier layer and the lattice constant of the well layer with thickness distribution and by averaging the result.

7. The device according to claim 6 , wherein

the well layer is provided in plurality, and

each well layer is disposed in each space between the barrier layers.

8. The device according to claim 1 , wherein

an equivalent lattice spacing of silicon which becomes a crystal substrate on which a crystal layer of at least either of the first semiconductor layer and the second semiconductor layer is grown is larger than the lattice constant of the first semiconductor layer.

9. The device according to claim 8 , wherein

a thermal expansion coefficient of a crystal of silicon which becomes a crystal substrate on which a crystal layer of at least either of the first semiconductor layer and the second semiconductor layer is grown is smaller than the thermal expansion coefficient of the first semiconductor layer.

10. The device according to claim 1 , wherein

an equivalent lattice spacing of silicon which becomes a crystal substrate on which a crystal layer of at least either of the first semiconductor layer and the second semiconductor layer is grown is larger than the lattice constant of the second semiconductor layer.

11. The device according to claim 10 , wherein

a thermal expansion coefficient of a crystal of silicon which becomes a crystal substrate on which a crystal layer of at least either of the first semiconductor layer and the second semiconductor layer is grown is smaller than the thermal expansion coefficient of the second semiconductor layer.

12. The device according to claim 1 , wherein

the light emitting layer has a layer including In, and

an average In composition of the light emitting layer is 4.0% or more, and

a thickness of the light emitting layer is 56 nanometers or more.

13. The device according to claim 1 , wherein

the light emitting layer has a layer including In, and

an average In composition of the light emitting layer is 4.5% or more, and

a thickness of the light emitting layer is 48 nanometers or more.

14. The device according to claim 1 , further comprising:

a support substrate provided on the side opposite to the light emitting layer of the second semiconductor layer, and the support substrate supporting the first stress application layer, the first semiconductor layer, the light emitting layer, and the second semiconductor layer.

15. The device according to claim 1 , further comprising:

a first electrode penetrating the first stress application layer and being electrically connected to the first semiconductor layer.

16. The device according to claim 1 , further comprising:

a second electrode electrically connected to the second semiconductor layer.

17. The device according to claim 16 , further comprising:

a reflective metal provided on the second semiconductor layer, wherein

the second electrode is electrically connected to the second semiconductor layer through the reflective metal.

18. The device according to claim 1 , further comprising:

a light extraction layer provided on the side opposite to the first semiconductor layer of the first stress application layer, wherein

an unevenness is provided on the surface on the side opposite to the first stress application layer of the light extraction layer.

19. The device according to claim 18 , wherein

the first stress application layer includes a plurality of layers; and

at least one of the layers included in the first stress application layer is not separated by the unevenness and is present as a continuous layer.

20. The device according to claim 1 , wherein

light emitted from the light emitting layer is projected to the outside through the first semiconductor layer and the first stress application layer.