Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device of an embodiment includes a p-type semiconductor substrate, a first P-well formed in the semiconductor substrate, and on which a plurality of memory cells is formed, an first N-well surrounding the first P-well and electrically separating the first P-well from the semiconductor substrate, a first negative voltage generation unit configured to generate a first negative voltage, a boost unit configured to boost a voltage and generate a boosted voltage, and a well voltage transmission unit connected to the first negative voltage generation unit, the boost unit, and the first P-well, and configured to switch a voltage between the first negative voltage and the boosted voltage, the voltage being applied to the first P-well.
1. A nonvolatile semiconductor memory device comprising:
a p-type semiconductor substrate;
a first P-well formed in the semiconductor substrate, a plurality of memory cells being formed on the first P-well;
a first N-well surrounding the first P-well, the first N-well electrically separating the first P-well from the semiconductor substrate;
a first negative voltage generation unit configured to generate a first negative voltage;
a boost unit configured to boost a voltage and generate a boosted voltage;
a well voltage transmission unit connected to the first negative voltage generation unit, the boost unit, and the first P-well, the well voltage transmission unit configured to switch a voltage being applied to the first P-well between the first negative voltage and the boosted voltage;
a second P-well formed in the semiconductor substrate, a bit line connection transistor connecting a bit line of the memory cells and a sense amplifier unit being formed on the second P-well; and
a second N-well surrounding the second P-well, the second N-well electrically separating the second P-well from the semiconductor substrate.
2. The device according to claim 1 , further comprising:
a second negative voltage generation unit configured to generate a second negative voltage to be applied to the bit line of the memory cells; and
a bit line switch unit configured to transfer the second negative voltage to the bit line.
3. The device according to claim 1 , further comprising:
a select gate transistor formed on the first P-well, the select gate transistor configured to select the memory cells;
a third P-well, a select gate switch unit configured to transfer a voltage to be applied to a gate electrode of the select gate transistor being formed on the third P-well; and
a third N-well surrounding the third P-well, the third N-well electrically separating the third P-well from the semiconductor substrate.
4. The device according to claim 1 , wherein the first negative voltage generation unit includes a charge pump circuit.
5. The device according to claim 1 , wherein the first negative voltage is −3 V or more and −1 V or less.
6. The device according to claim 1 , wherein the boosted voltage is 13 V or more and 26 V or less.
7. The device according to claim 3 , further comprising:
a fourth negative voltage generation unit configured to generate a fourth negative voltage to be applied to a word line of the memory cells; and
a word line switch unit configured to transfer the fourth negative voltage to the word line,
wherein the word line switch unit is formed on the third P-well.
8. The device according to claim 7 , wherein the fourth negative voltage is −3 V or more and −1 V or less.
9. The device according to claim 7 , wherein the fourth negative voltage is lower than the first negative voltage.
10. The device according to claim 1 , wherein the memory cells include a floating gate structure.
11. The device according to claim 1 , wherein the semiconductor substrate includes silicon.