Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device comprising:

a memory cell array connected to word lines and bit lines, and including memory cells each of which is capable of storing n values (n is a natural number of 3 or more); and

a controller configured to control voltages at a word line and a bit line according to write data, and to perform a write operation to write data to the memory cell and a verify operation to verify a threshold voltage of the memory cell, wherein

the controller is configured to perform a verify operation using a first verification voltage and a second verification voltage (first verification voltage<second verification voltage) when first value data is stored in a first memory cell,

the controller is configured to determine whether a write operation to the first memory cell is completed or continued based on write data of a second memory cell adjacent to the first memory cell when a threshold voltage of the first memory cell is greater than or equal to the first verification voltage and less than the second verification voltage,

the controller is configured to complete the write operation to the first memory cell when the threshold voltage of the first memory cell is greater than or equal to the first verification voltage and less than the second verification voltage, and when second value data is stored in the second memory cell, and

a threshold voltage of the second value data is greater than that of the first value data.

2. The device of claim 1 , wherein

the controller is configured to inhibit a write operation to a third memory cell having a threshold voltage greater than or equal to the second verification voltage, and

the controller is configured to set the first memory cell in which the write operation is completed to a bias identical to that of the third memory cell.

3. The device of claim 1 , wherein

the controller is configured to continue the write operation to the first memory cell when the threshold voltage of the first memory cell is greater than or equal to the first verification voltage and less than the second verification voltage, and when third value data is stored in the second memory cell, and

a threshold voltage of the third value data is less than or equal to that of the first threshold voltage.

4. The device of claim 3 , wherein

the controller is configured to apply a middle voltage to a bit line connected to the first memory cell when the write operation to the first memory cell is continued, and

the middle voltage is set between a first bit line voltage that is used to write data to a memory cell having a threshold voltage less than the first verification voltage and a second bit line voltage (first bit line voltage<second bit line voltage) that is used to inhibit the write operation to the memory cell.

5. The device of claim 1 , wherein the controller is configured to continue the write operation to the first memory cell by applying a ground voltage to a bit line connected to the first memory cell when the threshold voltage of the first memory cell is less than the first verification voltage.

6. The device of claim 1 , further comprising a latch circuit storing write data and the verify result of the memory cell,

wherein the controller is configured to operate using the data of the latch circuit.

7. The device of claim 6 , wherein a first latch circuit connected to the first memory cell includes a data path to a second latch circuit connected to the second memory cell.

8. The device of claim 1 , wherein the first value data has a threshold voltage that is highest next to a threshold voltage in an erase state.

9. A nonvolatile semiconductor memory device comprising:

a memory cell array connected to word lines and bit lines, and including memory cells each of which is capable of storing four values corresponding to first to fourth value data, the first value data corresponding to an erase state; and

a controller configured to control voltages at a word line and a bit line according to write data, and to perform a write operation to write data to the memory cell and a verify operation to verify a threshold voltage of the memory cell, wherein

the controller is configured to perform a verify operation to verify the threshold voltage of a first memory cell using a first verification voltage and a second verification voltage (first verification voltage<second verification voltage) when the second value data is stored in the first memory cell,

the controller is configured to determine whether a write operation of the first memory cell is completed or continued based on write data of a second memory cell adjacent to the first memory cell when a threshold voltage of the first memory cell is greater than or equal to the first verification voltage and less than the second verification voltage,

the controller is configured to complete the write operation to the first memory cell when the threshold voltage of the first memory cell is greater than or equal to the first verification voltage and less than the second verification voltage, and when the fourth value data is stored in the second memory cell, and

the controller is configured to complete the write operation to the first memory cell when the threshold voltage of the first memory cell is greater than or equal to the second verification voltage.

10. The device of claim 9 , wherein

the controller is configured to inhibit a write operation to a third memory cell having a threshold voltage greater than or equal to the second verification voltage, and

the controller is configured to set the first memory cell in which the write operation is completed to a bias identical to that of the third memory cell.

11. The device of claim 9 , wherein

the controller is configured to continue the write operation to the first memory cell when the threshold voltage of the first memory cell is greater than or equal to the first verification voltage and less than the second verification voltage, and when the first, second, or third value data is stored in the second memory cell.

12. The device of claim 11 , wherein

the controller is configured to apply a middle voltage to a bit line connected to the first memory cell when the write operation to the first memory cell is continued, and

the middle voltage is set between a first bit line voltage that is used to write data to a memory cell having a threshold voltage less than the first verification voltage and a second bit line voltage (first bit line voltage<second bit line voltage) that is used to inhibit the write operation to the memory cell.

13. The device of claim 9 , wherein the controller is configured to continue the write operation to the first memory cell by applying a ground voltage to a bit line connected to the first memory cell when the threshold voltage of the first memory cell is less than the first verification voltage.

14. The device of claim 9 , further comprising a latch circuit storing write data and the verify result of the memory cell,

wherein the controller is configured to operate using the data of the latch circuit.

15. The device of claim 14 , wherein a first latch circuit connected to the first memory cell includes a data path to a second latch circuit connected to the second memory cell.

16. The device of claim 14 , wherein the second verification voltage is a voltage at which a verify operation for the second value data is passed.