Low power memory device with JFET device structures
View Patent ↗There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based isolation.
1. A method of manufacturing comprising:
forming a diffusion based isolation region to electrically isolate a plurality of JFET access devices;
forming a channel region of a JFET access device of the plurality of JFET access devices in an area created by the diffusion based isolation region;
forming a gate of the JFET access device over and in physical contact with the channel region; and
forming a memory element in the same plane as the gate or in a plane above the gate.
2. The method of claim 1 , wherein forming a diffusion based isolation region comprises:
forming mini-trenches;
filling the bottom of the mini-trenches with a material having a higher bandgap than the material in which the mini-trench is formed;
forming a thermal oxide in the mini-trench over the high bandgap material; and
diffusing ions into the thermal oxide to create a fixed charge.
3. The method of claim 1 , wherein forming the channel region comprises forming a PNP channel region.
4. The method of claim 1 , wherein forming the channel region comprises forming a recessed channel region.
5. The method of claim 4 , wherein forming the gate region comprises forming a gate in the recessed channel region.
6. The method of claim 1 , wherein forming the channel region comprises forming a Fin channel region.
7. The method of claim 6 , wherein forming the gate region comprises forming a gate that covers three sides of the channel.
8. The method of claim 1 , comprising forming drain and source regions.
9. A method of manufacturing comprising:
forming a Fin channel region of a JFET access device in a semiconductor substrate;
forming a gate of the JFET access device directly over the Fin channel region; and
forming a capacitive memory element electrically coupled to the JFET access device.
10. The method of claim 9 , comprising forming a passivation material over the gate.
11. The method of claim 9 , wherein the semiconductor substrate comprises a dopant concentration less than or equal to approximately 1e 16 /cm 3 .
12. The method of claim 9 , wherein forming the Fin channel region comprises:
forming a recessed Fin channel region; and
forming a plurality of Fins, and wherein forming the gate comprises forming the gate over the recessed Fin channel region and the plurality of Fins.
13. A method of manufacturing comprising:
forming a gate of a JFET access device around a Fin channel region of the JFET access device, wherein there is no gate dielectric between the gate and the Fin channel region;
forming a source region of the JFET access device and a drain region of the JFET access device conductively coupled to the Fin channel region; and
forming a capacitive memory element electrically coupled to the JFET access device.
14. The method of claim 13 , wherein forming the gate comprises forming a gate having a generally cylindrical shape.
15. The method of claim 13 , wherein forming the gate comprises forming a gate having a generally cubical shape.
16. The method of claim 13 , wherein the Fin channel region comprises a dopant concentration less than or equal to approximately 1e 16 /cm 3 .
17. A method of manufacturing comprising:
forming a Fin channel region;
forming a gate directly on the surface of the Fin channel region, wherein the gate extends from the Fin channel region only in an x-direction; and
forming an elevated source region and an elevated drain region on the Fin channel region, wherein the elevated source region and the elevated drain region extend above the Fin channel region and above the gate only in a z-direction, and wherein the z-direction is substantially perpendicular to the x-direction and to the substrate, and the x-direction is substantially parallel to the substrate.
18. The method of claim 17 , wherein forming the gate comprises forming the gate directly on two sides of the Fin channel region.
19. The method of claim 17 , wherein the Fin channel region comprises a dopant concentration less than or equal to approximately 1e 16 /cm 3 .