Optimized mechanism to simplify the circulant shifter and the P/Q kick out for layered LDPC decoder
A layered LDPC decoder architecture includes a single MUX and a single shifter element for processing an optimized LDPC parity check matrix. The optimized LDPC parity check matrix may be a K×L sub-matrix having zero elements, non-zero elements defined by a circulant matrix or zero matrices, and identity matrixes.
1. A method for decoding a LDPC encoded signal in a layered architecture, comprising:
bit-shifting, with a computer processor, a first signal based on a delta shift value;
selecting, with a computer processor, a signal from the bit-shifted first signal and a second combined signal, wherein the second combined signal is a combination of at least two signals; and
storing the selected signal in a ping-pong memory designated for storing some combination of P type messages, Q type messages and log likelihood ratios (LPQ memory).
2. The method of claim 1 , further comprising:
comparing, with a computer processor, bits in the bit-shifted first signal to one or more check nodes to produce a Q sign signal comprising Q sign bits; and
combining, with a computer processor, the Q sign signal and the bit-shifted first signal to produce the second combined signal.
3. The method of claim 2 , wherein the Q sign signal is used by a capacitance-to-voltage generator before being combined with the bit-shifted first signal to generate at least a capacitance-to-voltage message.
4. The method of claim 1 , further comprising:
comparing, with a computer processor, bits in the bit-shifted first signal to one or more check nodes to produce a data set; and
combining, with a computer processor, the data set and a LPQ signal to produce the first signal.
5. The method of claim 1 , further comprising:
comparing, with a computer processor, bits in the bit-shifted first signal to produce a data set; and
combining, with a computer processor, the data set and a LPQ signal to produce an updated first signal.
6. The method of claim 5 , wherein the data set is used by a capacitance-to-voltage generator before being combined with the first signal to generate at least a voltage.
7. The method of claim 1 , further comprising:
bit-shifting, with a computer processor, the selected signal based on a second delta shift value from a delta shift value matrix;
comparing, with a computer processor, bits in the bit-shifted selected signal to produce a Q sign signal comprising Q sign bits and a data set;
combining, with a computer processor, the Q sign signal and the bit-shifted selected signal to produce a Q type signal comprising a Q type message; and
selecting, with a computer processor, an updated LPQ signal from the bit-shifted selected signal and the Q type signal.
8. An apparatus for decoding a LDPC encoded signal, comprising:
a processor;
a memory connected to the processor, at least a portion of the memory comprising a ping-pong memory designated for storing some combination of P type messages, Q type messages and log likelihood ratios; and
computer executable program code configured to execute on the processor,
wherein the computer executable program code is configured to instruct the processor to:
bit-shift a first signal based on a delta shift value;
select a signal from the bit-shifted first signal and a second combined signal; and
store the selected signal in the memory.
9. The apparatus of claim 8 , wherein the computer executable program code is further configured to instruct the processor to:
compare bits in the bit-shifted first signal to produce a Q sign signal comprising Q sign bits; and
combine the Q sign signal and the bit-shifted first signal to produce the second combined signal.
10. The apparatus of claim 9 , wherein the computer executable program code is further configured to instruct the processor to utilize the Q sign signal with a capacitance-to-voltage generator before combining the Q sign signal with the bit-shifted first signal to generate at least a capacitance-to-voltage message.
11. The apparatus of claim 8 , wherein the computer executable program code is further configured to instruct the processor to:
compare bits in the bit-shifted first signal to produce a data set; and
combine the data set and a LPQ signal to produce the first signal.
12. The apparatus of claim 8 , wherein the computer executable program code is further configured to instruct the processor to:
compare bits in the bit-shifted first signal to produce a data set; and
combine the data set and a LPQ signal to produce an updated first signal.
13. The apparatus of claim 12 , wherein the computer executable program code is further configured to instruct the processor to utilize the data set before combining the data set with the first signal to generate at least a voltage based on the data set.
14. The apparatus of claim 8 , wherein the computer executable program code is further configured to instruct the processor to:
bit-shift the selected signal based on a second delta shift value from a delta shift value matrix;
compare bits in the bit-shifted selected signal to produce a Q sign signal comprising Q sign bits and a data set;
combine the Q sign signal and the bit-shifted selected signal to produce a Q type signal comprising a Q type message; and
select an updated LPQ signal from the bit-shifted selected signal and the Q type signal.
15. An apparatus for decoding a LDPC encoded signal, comprising:
a ping-pong memory designated for storing some combination of P type messages, Q type messages and log likelihood ratios (LPQ memory);
a first additive element connected to the LPQ memory;
a shifter connected to the first additive element;
a second additive element connected to the shifter; and
a multiplexer connected to the shifter, the second additive element and the LPQ memory,
wherein:
the shifter is configured to receive a first signal from the LPQ memory and receive a delta shift value;
the shifter is configured to send a bit-shifted first signal to the multiplexer and the second additive element;
the second additive element is configured to send a Q type signal comprising a Q type message to the multiplexer; and
the multiplexer is configured to send a multiplexed signal to the LPQ memory, wherein the multiplexed signal includes a signal resulting from the combination of at least two signals.
16. The apparatus of claim 15 , further comprising a CNU array connected to the second additive element for comparing bits in the bit-shifted first signal to produce a Q sign signal comprising Q sign bits,
wherein the second additive element is configured to combine the Q sign signal and the bit-shifted first signal to produce the Q type signal.
17. The apparatus of claim 16 , further comprising a first capacitance-to-voltage generator configured to use the Q sign signal to generate at least a capacitance-to-voltage message.
18. The apparatus of claim 15 , further comprising a CNU array connected to the second additive element for comparing bits in the bit-shifted first signal to produce a data set,
wherein the first additive element is configured to combine the data set signal and a LPQ signal to produce the first signal.
19. The apparatus of claim 18 , further comprising a first capacitance-to-voltage generator configured to use the data set to generate at least a voltage.
20. The apparatus of claim 15 , further comprising a CNU array connected to the second additive element for comparing bits in the bit-shifted selected signal to produce a Q sign signal comprising Q sign bits and a data set,
wherein,
the shifter is further configured to bit-shift the selected signal based on a second delta shift value from a delta shift value matrix;
the second additive element is configured to combine a Q sign signal and the bit-shifted selected signal to produce an updated Q type signal comprising a Q type message; and
the multiplexer is configured to select an updated LPQ signal from the bit-shifted selected signal and the updated Q type signal.