Thyristor-based memory cells, devices and systems including the same and methods for forming the same
View Patent ↗Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F 2 , and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate. The control gate may be electrically coupled with one or more of the thyristors and may be operably coupled to a voltage source. The thyristor-based memory cells may be formed in an array on a conductive strap, which may function as a cathode or a data line. A system may be formed by integrating the semiconductor devices with one or more memory access devices or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.
1. A method of forming a semiconductor device, comprising:
forming a semiconductor structure comprising amorphous silicon overlying an electrically insulative material, a conductive material overlying the amorphous silicon, a doped material overlying the conductive material and a doped crystalline silicon overlying the doped material;
removing portions of each of the doped crystalline silicon, the doped material, the conductive material and the amorphous silicon to form a plurality of channels exposing the electrically insulative material;
removing portions of the doped crystalline silicon and the doped material to form a plurality of pillars, each pillar of the plurality of pillars including a first doped region and a second doped region oppositely doped with respect to the first doped region;
forming at least one control gate on at least one surface of each pillar of the plurality of pillars;
exposing the plurality of pillars to a first dopant to form a third doped region, oppositely doped with respect to the second doped region; and
exposing the plurality of pillars to a second dopant to form a fourth doped region.
2. The method of claim 1 , further comprising forming at least one conductive line over and in contact with the fourth doped region of each pillar of the plurality of pillars.
3. The method of claim 1 , wherein forming at least one control gate on at least one surface of each pillar of the plurality of pillars comprises forming the control gate over a surface of one of the second and third doped regions.
4. The method of claim 1 , wherein forming a semiconductor structure comprising amorphous silicon overlying an electrically insulative material, a conductive material overlying the amorphous silicon, a doped material overlying the conductive material and a doped crystalline silicon overlying the doped material comprises:
forming a donor wafer comprising the amorphous silicon overlying the conductive material, the conductive material overlying the doped material disposed on a crystalline silicon wafer;
implanting ions to a predetermined depth into the crystalline silicon wafer;
attaching the amorphous silicon of the donor wafer to the electrically insulative material on an acceptor wafer; and
separating a portion of the donor wafer to leave a portion of the crystalline silicon wafer, the doped material, the conductive material, and the amorphous silicon overlying a surface of the electrically insulative material of the acceptor wafer.
5. The method of claim 1 , wherein forming a semiconductor structure further comprises forming a semiconductor structure comprising a logic device formed on a wafer underlying the electrically insulative material.
6. The method of claim 1 , wherein removing portions of each of the doped crystalline silicon, the doped material, the conductive material and the amorphous silicon to form a plurality of channels exposing the electrically insulative material comprises forming the plurality of channels extending in a first direction.
7. The method of claim 6 , wherein removing portions of the doped crystalline silicon and the doped material to form a plurality of pillars comprises removing material in a second direction substantially perpendicular to the first direction.
8. The method of claim 1 wherein the conductive material comprises at least one of a phase change material, titanium, titanium silicide, titanium oxide, titanium nitride, tantalum, tantalum silicide, tantalum oxide, tantalum nitride, tungsten, tungsten silicide, tungsten oxide, aluminum, and tungsten nitride.
9. The method of claim 1 wherein the amorphous silicon is formed by PVD.
10. The method of claim 1 wherein an outer surface of the amorphous silicon is treated with plasma.
11. The method of claim 1 wherein an outer surface of the amorphous silicon is treated with at least one of ammonium hydroxide or hydrogen fluoride.