Use of emerging non-volatile memory elements with flash memory
View Patent ↗Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array.
1. A system comprising:
a processor; and
a memory device coupled to said processor, said memory device comprising an array of transistor-based non-volatile memory having emerging non-volatile memory for storing programming data into the array via sense circuitry.
2. The system of claim 1 , wherein the emerging non-volatile memory comprises one of phase change memory, magnetoresistive memory, resistive memory, ferroelectric memory, spin-transfer-torque memory, or nano-tube memory.
3. The system of claim 1 , wherein the array comprises a NAND flash memory array that is organized into a plurality of blocks having a block size, and wherein the emerging non-volatile memory is organized into at least one block having the block size.
4. The system of claim 1 , wherein bit lines of the emerging non-volatile memory connects to bit lines of the array of transistor-based non-volatile memory.
5. The system of claim 1 , wherein the emerging non-volatile memory stores blocks of data.
6. The system of claim 5 , wherein the blocks of data are used as cache memory.
7. A system comprising:
a processor; and
a memory device coupled to the processor, said memory device comprising:
an array of first emerging non-volatile memory elements, the array being organized into a plurality of memory blocks, each memory block comprising a plurality of memory pages, and
a cache memory circuit electrically coupled to the array, the cache memory circuit comprising a second emerging non-volatile memory element for storing programming data in the array of first emerging non-volatile memory elements using sense circuitry, wherein the second emerging non-volatile memory element is organized into at least one memory block.
8. The system of claim 7 , wherein the array and the cache memory circuit are in a same module.
9. The system of claim 7 , wherein the array and the cache memory circuit are on a same circuit board.
10. The system of claim 7 , wherein the cache memory circuit is stacked with the array in a same chip package.
11. The system of claim 7 , wherein the first and second emerging non-volatile memory elements comprise one of phase change memory elements, magnetoresistive memory elements, resistive memory elements, ferroelectric memory elements, spin-transfer-torque memory elements, or nano-tube memory elements.
12. A system comprising:
a processor; and
a memory device coupled to the processor, said memory device comprising:
an array of transistor-based non-volatile memory elements, and
a circuit comprising sense circuitry coupled to the array, the sense circuitry comprising a data latch and a cache latch where each of the latches include emerging non-volatile memory elements and store data to be stored in the array and/or store data that was previously stored in the array.
13. The system of claim 12 , wherein the emerging non-volatile memory elements comprise one of phase change memory elements, magnetoresistive memory elements, resistive memory elements, ferroelectric memory elements, spin-transfer-torque memory elements, or nano-tube memory elements.
14. The system of claim 12 , wherein the array comprises a NAND flash memory and is organized into a plurality of pages having a page size, and wherein a number of the plurality of emerging non-volatile memory elements is equal to the page size.
15. The system of claim 12 , wherein the array comprises a NAND flash memory array and is organized into a plurality of blocks having a block size, and wherein the plurality of emerging non-volatile memory elements are organized into at least one block having the block size.
16. The system of claim 12 , wherein the array comprises a NAND flash memory array and is organized into a plurality of blocks having a block size, and wherein the plurality of emerging non-volatile memory elements are organized into more than one block having the block size.
17. A system comprising:
a processor; and
a memory device coupled to the processor, said memory device comprising:
an array of transistor based non-volatile memory cells, the array being organized into a plurality of memory blocks, each memory block comprising a plurality of memory pages, and
a cache memory circuit electrically coupled to the array, the cache memory circuit comprising laches where the laches are a plurality of emerging non-volatile memory elements for storing data to be stored in the array, and the emerging non-volatile memory elements are organized into at least one memory block.
18. The system of claim 17 , wherein the emerging non-volatile memory elements are organized into a plurality of memory blocks.
19. The system of claim 18 , wherein data stored in the memory blocks is error corrected before being programmed into a memory block in the array.
20. The system of claim 18 , wherein data stored in the memory blocks undergoes fragment fixing before being programmed into a memory block in the array.
21. The system of claim 18 , wherein at least one block of emerging non-volatile memory is used as a redundant block for a bad memory block in the array.